# `addiw`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/addiw

**Add immediate word (32-bit)** · RV64 only

Category: Arithmetic

Adds a signed 12-bit immediate to the low 32 bits of the second register and sign-extends the sum into the first.

[RISC-V manual: addiw](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv64.html#norm:addiw_op)

## Forms

- `addiw t1, t2, imm12`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.

## Example

```riscv64
.text
li t0, 2147483647
# t0=2147483647, immediate 1; addiw writes -2147483648 (0xFFFFFFFF80000000) to t2.
addiw t2, t0, 1
```