# `addw`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/addw

**Add word (32-bit)** · RV64 only

Category: Arithmetic

Adds the low 32 bits of the second and third registers and sign-extends the 32-bit sum into the first.

[RISC-V manual: addw](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv64.html#norm:addw_subw_op)

Used in: [Going 64-bit](https://asm-editor.specy.app/learn/courses/risc-v/introduction/going-64-bit.md) (RISC-V assembly)

## Forms

- `addw t1, t2, t3`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `t3`: An integer register. It may be the same register as `t1`.

## Example

```riscv64
.text
li t0, 2147483647
li t1, 1
# t0=2147483647, t1=1; addw writes -2147483648 (0xFFFFFFFF80000000) to t2.
addw t2, t0, t1
```