# `andi`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/andi

**Bitwise AND immediate**

Category: Logic

Sets the first register to the bitwise AND of the second and a sign-extended 12-bit immediate.

[RISC-V manual: andi](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:andi_ori_xori_op)

Used in: [Arithmetic, logic and bits](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arithmetic-logic-and-bits.md) (RISC-V assembly), [The bitmap display and the keyboard registers](https://asm-editor.specy.app/learn/courses/risc-v/talking-to-the-outside-world/the-bitmap-display-and-the-keyboard.md) (RISC-V assembly), [Even or odd, count the set bits, multiply by shifting](https://asm-editor.specy.app/learn/courses/risc-v/examples/bit-tricks.md) (RISC-V assembly), [Move a square with the keyboard](https://asm-editor.specy.app/learn/courses/risc-v/examples/keyboard-control.md) (RISC-V assembly), [The snake game](https://asm-editor.specy.app/learn/courses/risc-v/examples/snake.md) (RISC-V assembly), [Flappy ASM](https://asm-editor.specy.app/learn/courses/risc-v/examples/flappy-asm.md) (RISC-V assembly), [Sampled sound](https://asm-editor.specy.app/learn/courses/risc-v/examples/sampled-sound.md) (RISC-V assembly)

## Forms

- `andi t1, t2, imm12`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.

## Example

```riscv
.text
li t0, 13
# t0=13, immediate 5; andi writes 5 to t2.
andi t2, t0, 5
```