# `csrr`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/csrr

**Read control and status register** · Pseudo-instruction

Category: System

Reads the CSR into a register without writing to the CSR.

[RISC-V manual: csrrs](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrs_op)

Used in: [When an instruction cannot be carried out](https://asm-editor.specy.app/learn/courses/risc-v/talking-to-the-outside-world/exceptions.md) (RISC-V assembly)

## Forms

- `csrr t1, csr`
  - `csrr t1, fcsr` → `csrrs t1, csr, zero`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `csr`: A control and status register, written by name or number, such as `fcsr`, `fflags`, `frm`, `cycle`, `time`, `instret`, `ustatus`, `uepc`, `ucause` or `utval`. See the [supported registers](https://asm-editor.specy.app/documentation/risc-v/registers.md).

## Example

```riscv
# Clear fcsr with the documented alias, then read it with csrr. t0 is 0.
.text
li t1, 0
csrw t1, fcsr
csrr t0, fcsr
```