# `csrrc`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/csrrc

**Atomic read/clear CSR**

Category: System

Reads the CSR into the first register and clears the CSR bits that are set in the last register, as one atomic step.

[RISC-V manual: csrrc](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrc_op)

## Forms

- `csrrc t0, csr, t1`

## Operands

- `t0`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `csr`: A control and status register, written by name or number, such as `fcsr`, `fflags`, `frm`, `cycle`, `time`, `instret`, `ustatus`, `uepc`, `ucause` or `utval`. See the [supported registers](https://asm-editor.specy.app/documentation/risc-v/registers.md).
- `t1`: An integer register. It may be the same register as `t0`.

## Example

```riscv
# Initialize fcsr=1; csrrc returns old fcsr in t0 and leaves fcsr=0.
.text
li t3, 1
csrw t3, fcsr
li t1, 1
csrrc t0, fcsr, t1
```