# `csrrsi`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/csrrsi

**Atomic read/set CSR immediate**

Category: System

Reads the CSR into a register and sets the CSR bits that are set in a 5-bit constant, as one atomic step.

[RISC-V manual: csrrsi](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrwi_csrrsi_csrrci_ops)

## Forms

- `csrrsi t0, csr, imm5`

## Operands

- `t0`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `csr`: A control and status register, written by name or number, such as `fcsr`, `fflags`, `frm`, `cycle`, `time`, `instret`, `ustatus`, `uepc`, `ucause` or `utval`. See the [supported registers](https://asm-editor.specy.app/documentation/risc-v/registers.md).
- `imm5`: An unsigned 5-bit immediate, `0` to `31`, used for values such as a shift count or a CSR immediate.

## Example

```riscv
# Initialize fcsr=0; csrrsi returns old fcsr in t0 and leaves fcsr=1.
.text
li t3, 0
csrw t3, fcsr
csrrsi t0, fcsr, 1
```