# `csrs`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/csrs

**Set bits in control and status register** · Pseudo-instruction

Category: System

Sets the CSR bits that are set in a register, leaving the other bits unchanged.

[RISC-V manual: csrrs](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrs_op)

## Forms

- `csrs t1, csr`
  - `csrs t1, fcsr` → `csrrs zero, csr, t1`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `csr`: A control and status register, written by name or number, such as `fcsr`, `fflags`, `frm`, `cycle`, `time`, `instret`, `ustatus`, `uepc`, `ucause` or `utval`. See the [supported registers](https://asm-editor.specy.app/documentation/risc-v/registers.md).

## Example

```riscv
# Initialize fcsr to 0, apply csrs with mask 1, then read fcsr into t2 (1).
.text
li t3, 0
csrw t3, fcsr
li t1, 1
csrs t1, fcsr
csrr t2, fcsr
```