# `csrsi`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/csrsi

**Set bits in CSR immediate** · Pseudo-instruction

Category: System

Sets the CSR bits that are set in a 5-bit constant, leaving the other bits unchanged.

[RISC-V manual: csrrsi](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrwi_csrrsi_csrrci_ops)

Used in: [When an instruction cannot be carried out](https://asm-editor.specy.app/learn/courses/risc-v/talking-to-the-outside-world/exceptions.md) (RISC-V assembly)

## Forms

- `csrsi csr, imm12`
  - `csrsi fcsr, 100` → `csrrsi zero, csr, imm12`

## Operands

- `csr`: A control and status register, written by name or number, such as `fcsr`, `fflags`, `frm`, `cycle`, `time`, `instret`, `ustatus`, `uepc`, `ucause` or `utval`. See the [supported registers](https://asm-editor.specy.app/documentation/risc-v/registers.md).
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.

## Example

```riscv
# Initialize fcsr to 0; csrsi uses immediate 1 and leaves fcsr=1.
.text
li t3, 0
csrw t3, fcsr
csrsi fcsr, 1
csrr t2, fcsr
```