# `csrw`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/csrw

**Write control and status register** · Pseudo-instruction

Category: System

Writes a register into the CSR and discards the value the CSR held before.

[RISC-V manual: csrrw](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrw_op)

Used in: [When an instruction cannot be carried out](https://asm-editor.specy.app/learn/courses/risc-v/talking-to-the-outside-world/exceptions.md) (RISC-V assembly)

## Forms

- `csrw t1, csr`
  - `csrw t1, fcsr` → `csrrw zero, csr, t1`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `csr`: A control and status register, written by name or number, such as `fcsr`, `fflags`, `frm`, `cycle`, `time`, `instret`, `ustatus`, `uepc`, `ucause` or `utval`. See the [supported registers](https://asm-editor.specy.app/documentation/risc-v/registers.md).

## Example

```riscv
# Initialize fcsr to 0, apply csrw with mask 1, then read fcsr into t2 (1).
.text
li t3, 0
csrw t3, fcsr
li t1, 1
csrw t1, fcsr
csrr t2, fcsr
```