# `csrwi`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/csrwi

**Write CSR immediate** · Pseudo-instruction

Category: System

Writes a 5-bit constant into the CSR and discards the value it held before.

[RISC-V manual: csrrwi](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrwi_csrrsi_csrrci_ops)

## Forms

- `csrwi csr, imm12`
  - `csrwi fcsr, 100` → `csrrwi zero, csr, imm12`

## Operands

- `csr`: A control and status register, written by name or number, such as `fcsr`, `fflags`, `frm`, `cycle`, `time`, `instret`, `ustatus`, `uepc`, `ucause` or `utval`. See the [supported registers](https://asm-editor.specy.app/documentation/risc-v/registers.md).
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.

## Example

```riscv
# Initialize fcsr to 0; csrwi uses immediate 1 and leaves fcsr=1.
.text
li t3, 0
csrw t3, fcsr
csrwi fcsr, 1
csrr t2, fcsr
```