# `divu`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/divu

**Divide unsigned**

Category: Arithmetic

Divides the second register by the third as unsigned integers and stores the quotient in the first.

[RISC-V manual: divu](https://docs.riscv.org/reference/isa/v20260120/unpriv/m-st-ext.html#norm:div_divu_op)

Used in: [Arithmetic, logic and bits](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arithmetic-logic-and-bits.md) (RISC-V assembly), [Flappy ASM](https://asm-editor.specy.app/learn/courses/risc-v/examples/flappy-asm.md) (RISC-V assembly)

## Forms

- `divu t1, t2, t3`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `t3`: An integer register. It may be the same register as `t1`.

## Example

```riscv
.text
li t0, 18
li t1, 5
# t0=18, t1=5; divu writes 3 to t2.
divu t2, t0, t1
```