# `divuw`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/divuw

**Divide unsigned word (32-bit)** · RV64 only

Category: Arithmetic

Divides the low 32 bits of the second register by those of the third as unsigned values and sign-extends the quotient into the first.

[RISC-V manual: divuw](https://docs.riscv.org/reference/isa/v20260120/unpriv/m-st-ext.html#norm:divw_divuw_op)

## Forms

- `divuw t1, t2, t3`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `t3`: An integer register. It may be the same register as `t1`.

## Example

```riscv64
.text
li t0, 18
li t1, 5
# t0=18, t1=5; divuw writes 3 to t2.
divuw t2, t0, t1
```