# `fence`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/fence

**Memory fence**

Category: Atomic

Makes memory and I/O accesses before the fence take effect before those after it, as other threads see them.

[RISC-V manual: fence](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:fence_op)

## Forms

- `fence imm5, imm5`

## Operands

- `imm5`: An unsigned 5-bit immediate, `0` to `31`, used for values such as a shift count or a CSR immediate.

## Example

```riscv
# Store 42, order reads and writes before reads and writes, then load 42 back. This single-threaded emulator cannot show ordering between harts.
.data
value: .word 0
.text
la t0, value
li t1, 42
sw t1, 0(t0)
fence 3, 3
lw t2, 0(t0)
```