# `jr`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/jr

**Jump register** · Pseudo-instruction

Category: Control flow

Jumps to the address held in a register.

[RISC-V manual: jalr](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:jalr_op)

Used in: [if, else and jump tables](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/if-else-and-jump-tables.md) (RISC-V assembly), [A jump table](https://asm-editor.specy.app/learn/courses/risc-v/examples/jump-table.md) (RISC-V assembly), [Chiptune](https://asm-editor.specy.app/learn/courses/risc-v/examples/chiptune.md) (RISC-V assembly)

## Forms

- `jr t0`
  - `jr t0` → `jalr zero, t0, 0`
- `jr t0, imm12`
  - `jr t0, -100` → `jalr zero, t0, imm12`

## Operands

- `t0`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.

## Example

```riscv
# jr transfers to done; the skipped instruction would add 100 to t2.
.text
li t2, 0
la t3, done
jr t3
addi t2, t2, 100
done:
addi t2, t2, 1
# t2=1 confirms the named transfer reached done.
```