# `lhu`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/lhu

**Load halfword unsigned**

Category: Load and store

Loads the 16-bit halfword at the address in the second register plus an offset into the first, zero-extended to the register width.

[RISC-V manual: lhu](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:lhu_op)

Used in: [Chiptune](https://asm-editor.specy.app/learn/courses/risc-v/examples/chiptune.md) (RISC-V assembly), [Sampled sound](https://asm-editor.specy.app/learn/courses/risc-v/examples/sampled-sound.md) (RISC-V assembly)

## Forms

- `lhu t1, imm12(t2)`

## Pseudo-instructions

The processor does not have these forms. The assembler replaces each of them with one or more real instructions. Open a row to see them.

- `lhu t1, (t2)`
  - `lhu t1,(t2)` → `lhu t1, 0(t2)`
- `lhu t1, imm`
  - `lhu t1,-100` → `lhu t1, imm(zero)`
  - `lhu t1,10000000` → `lui t1, hi(imm)`; `lhu t1, lo(imm)(t1)`
- `lhu t1, label`
  - `lhu t1,label` → `auipc t1, pcrel_hi(label)`; `lhu t1, pcrel_lo(label)(t1)`

- `lhu t1, %lo(label)(t2)` · Load from Address
  - `lhu t1,%lo(label)(t2)` → `lhu t1, lo(label)(t2)`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm`: An immediate value: a signed 12-bit value (`-2048` to `2047`) or a 32-bit value (`-2147483648` to `4294967295`). The size your value needs decides which real instructions the assembler uses. Open the row to see them for each size.
- `label`: A named address in the program, such as the start of a loop or a variable in `.data`.

## Example

```riscv
# value is initialized and naturally aligned for this operation.
.data
value: .word 0x017fff80
.text
la t0, value
# The first halfword is 0xFF80; lhu writes 65408 to t2.
lhu t2, 0(t0)
```