# `lw`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/lw

**Load word**

Category: Load and store

Loads the 32-bit word at the address in the second register plus an offset into the first, sign-extended on RV64.

[RISC-V manual: lw](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:lw_op)

Used in: [Loads, stores and immediates](https://asm-editor.specy.app/learn/courses/risc-v/introduction/loads-stores-and-immediates.md) (RISC-V assembly), [.data, .text and directives](https://asm-editor.specy.app/learn/courses/risc-v/introduction/data-text-and-directives.md) (RISC-V assembly), [Going 64-bit](https://asm-editor.specy.app/learn/courses/risc-v/introduction/going-64-bit.md) (RISC-V assembly), [Memory regions and executable files](https://asm-editor.specy.app/learn/courses/risc-v/introduction/memory-regions-and-executable-files.md) (RISC-V assembly), [if, else and jump tables](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/if-else-and-jump-tables.md) (RISC-V assembly), [Loops](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/loops.md) (RISC-V assembly), [Arrays and strings](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arrays-and-strings.md) (RISC-V assembly), [The stack and sp](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/the-stack-and-sp.md) (RISC-V assembly), [jal, ret and the calling convention](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/jal-ret-and-the-calling-convention.md) (RISC-V assembly), [Floating point and the F and D extensions](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/floating-point-and-the-f-and-d-extensions.md) (RISC-V assembly)

## Forms

- `lw t1, imm12(t2)`

## Pseudo-instructions

The processor does not have these forms. The assembler replaces each of them with one or more real instructions. Open a row to see them.

- `lw t1, (t2)`
  - `lw t1,(t2)` → `lw t1, 0(t2)`
- `lw t1, imm`
  - `lw t1,-100` → `lw t1, imm(zero)`
  - `lw t1,10000000` → `lui t1, hi(imm)`; `lw t1, lo(imm)(t1)`

- `lw t1, label` · Set t1 to contents of memory word at label's address
  - `lw t1,label` → `auipc t1, pcrel_hi(label)`; `lw t1, pcrel_lo(label)(t1)`

- `lw t1, %lo(label)(t2)` · Load from Address
  - `lw t1,%lo(label)(t2)` → `lw t1, lo(label)(t2)`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm`: An immediate value: a signed 12-bit value (`-2048` to `2047`) or a 32-bit value (`-2147483648` to `4294967295`). The size your value needs decides which real instructions the assembler uses. Open the row to see them for each size.
- `label`: A named address in the program, such as the start of a loop or a variable in `.data`.

## Example

```riscv64
# value is initialized and naturally aligned for this operation.
.data
value: .word 0x817fff80
.text
la t0, value
# The word 0x817FFF80 sign-extends in RV64; lw writes −2122317952 (0xFFFFFFFF817FFF80) to t2.
lw t2, 0(t0)
```