# `lwu`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/lwu

**Load word unsigned** · RV64 only

Category: Load and store

Loads the 32-bit word at the address in the second register plus an offset into the first, zero-extended to 64 bits.

[RISC-V manual: lwu](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv64.html#norm:lwu_op)

Used in: [Going 64-bit](https://asm-editor.specy.app/learn/courses/risc-v/introduction/going-64-bit.md) (RISC-V assembly)

## Forms

- `lwu t1, imm12(t2)`

## Pseudo-instructions

The processor does not have these forms. The assembler replaces each of them with one or more real instructions. Open a row to see them.

- `lwu t1, %lo(label)(t2)` · Load from Address
  - `lwu t1,%lo(label)(t2)` → `lwu t1, lo(label)(t2)`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.
- `t2`: An integer register. It may be the same register as `t1`.
- `label`: A named address in the program, such as the start of a loop or a variable in `.data`.

## Example

```riscv64
# value is initialized and naturally aligned for this operation.
.data
value: .word 0x817fff80
.text
la t0, value
# The word 0x817FFF80 zero-extends to RV64; lwu writes 2172649344 (0x817FFF80) to t2.
lwu t2, 0(t0)
```