# `mulhsu`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/mulhsu

**Multiply high (signed × unsigned)**

Category: Arithmetic

Multiplies the second register, as signed, by the third, as unsigned, and stores the high register-width bits of the product in the first.

[RISC-V manual: mulhsu](https://docs.riscv.org/reference/isa/v20260120/unpriv/m-st-ext.html#norm:mulh_mulhu_mulhsu_op)

## Forms

- `mulhsu t1, t2, t3`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `t3`: An integer register. It may be the same register as `t1`.

## Example

```riscv
.text
li t0, -2147483648
li t1, 2
# t0=-2147483648 and t1=2; the high product is -1; mulhsu writes -1 (0xFFFFFFFF) to t2.
mulhsu t2, t0, t1
```