# `mulhu`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/mulhu

**Multiply high (unsigned × unsigned)**

Category: Arithmetic

Multiplies the second register by the third, both unsigned, and stores the high register-width bits of the product in the first.

[RISC-V manual: mulhu](https://docs.riscv.org/reference/isa/v20260120/unpriv/m-st-ext.html#norm:mulh_mulhu_mulhsu_op)

Used in: [Arithmetic, logic and bits](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arithmetic-logic-and-bits.md) (RISC-V assembly)

## Forms

- `mulhu t1, t2, t3`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `t3`: An integer register. It may be the same register as `t1`.

## Example

```riscv
.text
li t0, -1
li t1, 2
# t0=0xFFFFFFFF and t1=2; the unsigned high product is 1; mulhu writes 1 to t2.
mulhu t2, t0, t1
```