# `negw`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/negw

**Negate word (32-bit)** · Pseudo-instruction · RV64 only

Category: Arithmetic

Sets the first register to the negation of the low 32 bits of the second, sign-extended.

[RISC-V manual: subw](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv64.html#norm:addw_subw_op)

## Forms

- `negw t1, t2`
  - `negw t1, t2` → `subw t1, zero, t2`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.

## Example

```riscv64
.text
li t0, 13
# t0=13; negw writes -13 (0xFFFFFFFFFFFFFFF3) to t2.
negw t2, t0
```