# `rdcycle`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/rdcycle

**Read cycle counter** · Pseudo-instruction

Category: System

Reads the cycle counter into a register.

[RISC-V manual: csrrs](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrs_op)

## Forms

- `rdcycle t1`
  - `rdcycle t1` → `csrrs t1, cycle, zero`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.

## Example

```riscv
# Read the cycle counter twice. Inspect t2=0: the second unsigned reading did not decrease.
.text
rdcycle t0
rdcycle t1
bltu t1, t0, backwards # Test whether the second reading is lower, treating both as unsigned.
li t2, 0
j done # Keep t2=0 by skipping the alternate result block.
backwards:
li t2, 1
done:
```