# `rdcycleh`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/rdcycleh

**Read cycle counter (upper 32 bits)** · Pseudo-instruction

Category: System

Reads the upper 32 bits of the cycle counter into a register (RV32 only).

[RISC-V manual: csrrs](https://docs.riscv.org/reference/isa/v20260120/unpriv/zicsr.html#norm:csrrs_op)

## Forms

- `rdcycleh t1`
  - `rdcycleh t1` → `csrrs t1, cycleh, zero`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.

## Example

```riscv
# Read the upper 32 bits of the cycle counter twice. Inspect t2=0: the second unsigned reading did not decrease.
.text
rdcycleh t0
rdcycleh t1
bltu t1, t0, backwards # Test whether the second reading is lower, treating both as unsigned.
li t2, 0
j done # Keep t2=0 by skipping the alternate result block.
backwards:
li t2, 1
done:
```