# `sd`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/sd

**Store double word** · RV64 only

Category: Load and store

Stores the 64-bit value of the first register at the address in the second plus an offset.

[RISC-V manual: sd](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv64.html#norm:sd_sw_sh_sb_op_rv64i)

Used in: [Going 64-bit](https://asm-editor.specy.app/learn/courses/risc-v/introduction/going-64-bit.md) (RISC-V assembly)

## Forms

- `sd t1, imm12(t2)`

## Pseudo-instructions

The processor does not have these forms. The assembler replaces each of them with one or more real instructions. Open a row to see them.

- `sd t1, %lo(label)(t2)` · Store to Address
  - `sd t1,%lo(label)(t2)` → `sd t1, lo(label)(t2)`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.
- `t2`: An integer register. It may be the same register as `t1`.
- `label`: A named address in the program, such as the start of a loop or a variable in `.data`.

## Example

```riscv64
# value is initialized and naturally aligned for this operation.
.data
value: .dword 0
.text
la t0, value
li t1, 42
# Store 42 (bytes 2A 00 00 00 00 00 00 00) at value; inspect Memory.
sd t1, 0(t0)
```