# `seqz`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/seqz

**Set equal to zero** · Pseudo-instruction

Category: Comparison

Sets the first register to 1 if the second is zero, otherwise to 0.

[RISC-V manual: sltiu](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:slti_sltiu_op)

## Forms

- `seqz t1, t2`
  - `seqz t1,t2` → `sltiu t1, t2, 1`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.

## Example

```riscv
.text
li t0, 0
# t0=0; seqz writes 1 to t2.
seqz t2, t0
```