# `sgtz`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/sgtz

**Set greater than zero** · Pseudo-instruction

Category: Comparison

Sets the first register to 1 if the second is greater than zero, otherwise to 0.

[RISC-V manual: slt](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:slt_sltu_op)

## Forms

- `sgtz t1, t2`
  - `sgtz t1,t2` → `slt t1, zero, t2`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.

## Example

```riscv
.text
li t0, 1
# t0=1; sgtz writes 1 to t2.
sgtz t2, t0
```