# `slli`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/slli

**Shift left logical immediate**

Category: Shifts and rotates

Shifts the second register left by an immediate amount and stores the result in the first.

[RISC-V manual: slli](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:slli_op)

Used in: [Loads, stores and immediates](https://asm-editor.specy.app/learn/courses/risc-v/introduction/loads-stores-and-immediates.md) (RISC-V assembly), [if, else and jump tables](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/if-else-and-jump-tables.md) (RISC-V assembly), [Arithmetic, logic and bits](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arithmetic-logic-and-bits.md) (RISC-V assembly), [Arrays and strings](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arrays-and-strings.md) (RISC-V assembly), [The stack and sp](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/the-stack-and-sp.md) (RISC-V assembly), [The bitmap display and the keyboard registers](https://asm-editor.specy.app/learn/courses/risc-v/talking-to-the-outside-world/the-bitmap-display-and-the-keyboard.md) (RISC-V assembly), [The largest element](https://asm-editor.specy.app/learn/courses/risc-v/examples/max-of-an-array.md) (RISC-V assembly), [Even or odd, count the set bits, multiply by shifting](https://asm-editor.specy.app/learn/courses/risc-v/examples/bit-tricks.md) (RISC-V assembly), [A jump table](https://asm-editor.specy.app/learn/courses/risc-v/examples/jump-table.md) (RISC-V assembly), [Binary search](https://asm-editor.specy.app/learn/courses/risc-v/examples/binary-search.md) (RISC-V assembly)

## Forms

- `slli t1, t2, imm6`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm6`: An unsigned shift count or bit number: `0` to `63` in RV64, or `0` to `31` in RV32.

## Example

```riscv64
.text
li t0, 13
# t0=13, immediate 2; slli writes 52 to t2.
slli t2, t0, 2
```