# `slliw`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/slliw

**Shift left logical immediate word (32-bit)** · RV64 only

Category: Shifts and rotates

Shifts the low 32 bits of the second register left by an immediate amount and sign-extends the result into the first.

[RISC-V manual: slliw](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv64.html#norm:slliw_srliw_sraiw_op)

## Forms

- `slliw t1, t2, imm5`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm5`: An unsigned 5-bit immediate, `0` to `31`, used for values such as a shift count or a CSR immediate.

## Example

```riscv64
.text
li t0, 13
# t0=13, immediate 2; slliw writes 52 to t2.
slliw t2, t0, 2
```