# `slt`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/slt

**Set less than**

Category: Comparison

Sets the first register to 1 if the second is less than the third as signed integers, otherwise to 0.

[RISC-V manual: slt](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:slt_sltu_op)

Used in: [Arithmetic, logic and bits](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arithmetic-logic-and-bits.md) (RISC-V assembly), [The bigger of two numbers](https://asm-editor.specy.app/learn/courses/risc-v/examples/if-else.md) (RISC-V assembly)

## Forms

- `slt t1, t2, t3`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `t3`: An integer register. It may be the same register as `t1`.

## Example

```riscv
.text
li t0, 3
li t1, 5
# t0=3, t1=5; slt writes 1 to t2.
slt t2, t0, t1
```