# `sltiu`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/sltiu

**Set less than immediate unsigned**

Category: Comparison

Sets the first register to 1 if the second is less than a sign-extended 12-bit immediate as unsigned, otherwise to 0.

[RISC-V manual: sltiu](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:slti_sltiu_op)

## Forms

- `sltiu t1, t2, imm12`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm12`: A signed 12-bit immediate, `-2048` to `2047`.

## Example

```riscv
.text
li t0, 1
# t0=1 is below the sign-extended all-ones immediate when compared unsigned; sltiu writes 1 to t2.
sltiu t2, t0, -1
```