# `srli`

[RISC-V Documentation](https://asm-editor.specy.app/documentation/risc-v.md) › [Instructions](https://asm-editor.specy.app/documentation/risc-v/instruction.md)

Web page: https://asm-editor.specy.app/documentation/risc-v/instruction/srli

**Shift right logical immediate**

Category: Shifts and rotates

Shifts the second register right by an immediate amount, filling with zeros, and stores the result in the first.

[RISC-V manual: srli](https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html#norm:srli_op)

Used in: [Arithmetic, logic and bits](https://asm-editor.specy.app/learn/courses/risc-v/think-in-assembly/arithmetic-logic-and-bits.md) (RISC-V assembly), [Even or odd, count the set bits, multiply by shifting](https://asm-editor.specy.app/learn/courses/risc-v/examples/bit-tricks.md) (RISC-V assembly), [Binary search](https://asm-editor.specy.app/learn/courses/risc-v/examples/binary-search.md) (RISC-V assembly), [The snake game](https://asm-editor.specy.app/learn/courses/risc-v/examples/snake.md) (RISC-V assembly), [Flappy ASM](https://asm-editor.specy.app/learn/courses/risc-v/examples/flappy-asm.md) (RISC-V assembly), [Sampled sound](https://asm-editor.specy.app/learn/courses/risc-v/examples/sampled-sound.md) (RISC-V assembly)

## Forms

- `srli t1, t2, imm6`

## Operands

- `t1`: Any integer register, `x0` to `x31`, or its named alias, such as `zero`, `t0` or `t6`.
- `t2`: An integer register. It may be the same register as `t1`.
- `imm6`: An unsigned shift count or bit number: `0` to `63` in RV64, or `0` to `31` in RV32.

## Example

```riscv64
.text
li t0, 13
# t0=13, immediate 2; srli writes 3 to t2.
srli t2, t0, 2
```