# x86-64 Vector instructions

[x86-64 Documentation](https://asm-editor.specy.app/documentation/x86.md)

Web page: https://asm-editor.specy.app/documentation/x86/vector-instructions

The ymm registers and the AVX, AVX2, FMA and BMI instructions: which run here, how they treat the upper half of a register, which cross between 128-bit lanes, and how memory operands are sized and aligned.

13 entries, each with its own page of markdown:

- [Vector instructions](https://asm-editor.specy.app/documentation/x86/vector-instructions/overview.md): AVX (Advanced Vector Extensions) extends the x86 vector registers from 128 bits to 256 bits (ymm0 to ymm15) and introduces a three-operand syntax with a v…
- [Registers](https://asm-editor.specy.app/documentation/x86/vector-instructions/registers.md): There are sixteen 256-bit vector registers, ymm0 through ymm15.
- [Three operands](https://asm-editor.specy.app/documentation/x86/vector-instructions/three-operands.md): AVX instructions add a v prefix to the SSE mnemonic and take a separate destination register followed by two sources: Unlike two-operand SSE instructions…
- [Upper bits](https://asm-editor.specy.app/documentation/x86/vector-instructions/upper-bits.md): When an instruction writes to a 128-bit xmm register, what happens to the high half (bits 128–255) of the enclosing ymm register depends on whether you use the…
- [128-bit lanes](https://asm-editor.specy.app/documentation/x86/vector-instructions/lanes.md): Most 256-bit instructions treat a ymm register as two independent 128-bit halves (128-bit lanes), performing the same 128-bit operation on the low half and the…
- [Memory operands](https://asm-editor.specy.app/documentation/x86/vector-instructions/memory.md): A 256-bit memory operand is 32 bytes (yword in NASM), and a 128-bit memory operand is 16 bytes (oword).
- [Alignment](https://asm-editor.specy.app/documentation/x86/vector-instructions/alignment.md): Unaligned moves (vmovups, vmovupd, vmovdqu), broadcasts, and memory operands inside v-prefixed arithmetic, comparison, or shuffle instructions (vaddps ymm0,…
- [Instruction families](https://asm-editor.specy.app/documentation/x86/vector-instructions/families.md): Most vector mnemonics support both 128-bit (xmm) and 256-bit (ymm) operands: Family Representative mnemonics Notes ---------------------------…
- [FMA](https://asm-editor.specy.app/documentation/x86/vector-instructions/fma.md): Fused multiply-add (FMA3) instructions compute a * b + c with a single rounding step at the end, rather than rounding a * b first and rounding again after…
- [What runs](https://asm-editor.specy.app/documentation/x86/vector-instructions/what-runs.md): The emulator runs all VEX-encoded instructions from these extensions: Extension Examples -----------------…
- [Where AVX code comes from](https://asm-editor.specy.app/documentation/x86/vector-instructions/sources.md): You can run AVX code in two ways: 1.
- [CPUID](https://asm-editor.specy.app/documentation/x86/vector-instructions/cpuid.md): Although the emulator executes AVX, AVX2, FMA, and BMI instructions directly, its cpuid instruction reports a baseline x86-64 processor without those feature…
- [Floating-point results](https://asm-editor.specy.app/documentation/x86/vector-instructions/floating-point.md): Rounding modes: vroundps/vroundpd/vroundss/vroundsd (when bit 2 of the immediate is set), vcvtps2ph, and float-to-integer conversions (vcvtps2dq, vcvtpd2dq)…