# `srl`

[Z80 Documentation](https://asm-editor.specy.app/documentation/z80.md) › [Instructions](https://asm-editor.specy.app/documentation/z80/instruction.md)

Web page: https://asm-editor.specy.app/documentation/z80/instruction/srl

**Shift right logical**

Category: Shifts and rotates

Shifts a register or memory byte right one bit, copying bit 0 to C and putting zero into bit 7.

Used in: [8-bit and 16-bit arithmetic, logic and bits](https://asm-editor.specy.app/learn/courses/z80/think-in-assembly/arithmetic-logic-and-bits.md) (Z80 assembly), [Reverse a string in place](https://asm-editor.specy.app/learn/courses/z80/examples/reverse-a-string.md) (Z80 assembly), [Multiply and divide, with the remainder](https://asm-editor.specy.app/learn/courses/z80/examples/multiply-and-divide.md) (Z80 assembly), [Even or odd, count the set bits, multiply by shifting](https://asm-editor.specy.app/learn/courses/z80/examples/bit-tricks.md) (Z80 assembly), [Binary search](https://asm-editor.specy.app/learn/courses/z80/examples/binary-search.md) (Z80 assembly), [The snake game](https://asm-editor.specy.app/learn/courses/z80/examples/snake.md) (Z80 assembly), [Flappy ASM](https://asm-editor.specy.app/learn/courses/z80/examples/flappy-asm.md) (Z80 assembly)

## Flags

| Flag | Effect |
| --- | --- |
| S | set from the result |
| Z | set from the result |
| H | always 0 |
| P/V | holds the parity of the result |
| N | always 0 |
| C | set from the result |

## Forms

- `srl r` · 2 bytes · 8 cycles · The contents of `r` are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.
  - `srl b`
  - `srl c`
  - `srl d`
  - `srl e`
  - `srl h`
  - `srl l`
  - `srl a`

- `srl (hl)` · 2 bytes · 15 cycles · The contents of (HL) are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.

- `srl (ix+dd)` · 4 bytes · 23 cycles · The contents of the memory location pointed to by IX plus `dd` are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7.
  - `srl (ix+dd)`
  - `srl (iy+dd)`

## Undocumented

Left out of Zilog's manual, but the Z80 runs them, and so does this emulator.

- `srl (ix+dd), r` · 4 bytes · 23 cycles · The contents of the memory location pointed to by IX plus `dd` are shifted right one bit position. The contents of bit 0 are copied to the carry flag and a zero is put into bit 7. The result is then stored in `r`.
  - `srl (ix+dd), b`
  - `srl (ix+dd), c`
  - `srl (ix+dd), d`
  - `srl (ix+dd), e`
  - `srl (ix+dd), h`
  - `srl (ix+dd), l`
  - `srl (ix+dd), a`
  - `srl (iy+dd), b`
  - `srl (iy+dd), c`
  - `srl (iy+dd), d`
  - `srl (iy+dd), e`
  - `srl (iy+dd), h`
  - `srl (iy+dd), l`
  - `srl (iy+dd), a`

## Operands

- `r`: An 8-bit register: `a`, `b`, `c`, `d`, `e`, `h` or `l`.
- [`(hl)`](https://asm-editor.specy.app/documentation/z80/registers/operand-hl.md): The byte in memory at the address stored in `hl`.
- [`(ix+dd)`](https://asm-editor.specy.app/documentation/z80/registers/operand-ix-dd.md): The byte in memory at `ix + dd`, where `dd` is a signed displacement from `-128` to `127`, for example `(ix+5)` or `(ix-3)`. `(iy+dd)` works the same way.

## Example

```z80
        .org 0x8000
        ld b, 3
        srl b
        halt
```