M68K Addressing Modes

Effective addresses

<ea>

Direct

Dn, An, Rn

Indirect

(An)

Address-register displacement

d(An)

Indirect postincrement/predecrement

(An)+, -(An)

Immediate

#imm, Im, #<num>

Absolute memory address

abs, Ea/<label>

Address-register indexed

d(An,Xn)

Program-counter relative

d(PC), d(PC,Xn)

Status registers

sr, ccr

User stack pointer

usp

Control registers

Rc, vbr, sfc, dfc, msp, isp, cacr, caar

On the 68020

opt p=68020

Scaled index

(bd,An,Xn*k), (bd,PC,Xn*k)

Base displacements

(bd.w,An,Xn), (bd.l,An,Xn)

Memory indirect

([bd,An],Xn,od), ([bd,An,Xn],od), ([bd,PC],Xn,od), ([bd,PC,Xn],od)

On the 68020, square brackets request a pointer read. The processor adds the components inside the brackets, reads a 32-bit pointer from that address, then adds the components outside the brackets to obtain the final address. Even an instruction such as lea reads that pointer, although it does not read data at the final address. An inaccessible pointer location can therefore cause a bus error.
([bd,An,Xn],od) is preindexed: the index is inside, so it picks which pointer is read, as from a table of pointers.
([bd,An],Xn,od) is postindexed: the index is outside, so it is added to the pointer once it has been read, as to the start of an array.
messages below is a table of three pointers, each the address of a string. This program prints string number 2:
    opt p=68020
    lea messages, a0
    moveq #2, d1              ; string number 2
    lea ([a0,d1.w*4]), a1     ; a1 = the pointer at a0 + 2 × 4
    move.b #14, d0
    trap #15                  ; prints "two"
    simhalt

messages:
    dc.l zero, one, two
zero:   dc.b 'zero', 0
one:    dc.b 'one', 0
two:    dc.b 'two', 0([a0,d1.w*4]) works in three steps:
Inside the brackets: a0 + d1 × 4 is messages + 8, the third long of the table.
The long stored there is the address of two.
Nothing follows the brackets, so that address is the one the operand names. lea puts the address itself in a1, where move would read the bytes stored there.
In a postindexed operand, the index selects a location relative to the pointer read. Here current holds a table address, and the index selects a word in that table:
    opt p=68020
    moveq #1, d1
    move.w ([current],d1.w*2), d0   ; word 1 of the table current points at: d0 = 20
    simhalt

current:  dc.l scores_b             ; the table in use
scores_a: dc.w 1, 2, 3
scores_b: dc.w 10, 20, 30Changing the long at current to scores_a makes the same instruction read the other table. For a jump table, use a preindexed operand: jmp ([handlers,pc,d0.w*4]) jumps through pointer number d0 in handlers. Here handlers is a target address, following the usual PC-relative notation.

Suppressed registers

za0, zd0, zpc

Long branches

bra.l label, bsr.l label, b<cc>.l label

Register pairs

Dh:Dl, Dr:Dq, (Rn1):(Rn2), Dx:Dy, (Rx):(Ry)

Bit fields

{offset:width}, opt bit

A bit field is a run of 1 to 32 bits in a data register or in memory. It can hold a packed value, such as a 5-bit colour component, or part of a bitmap. The 68020’s bit-field instructions test, extract or change these bits directly.
Write {offset:width} immediately after the operand. The offset counts from bit 31 of a data register or bit 7 of the byte at the memory address. The width is the number of bits selected. For example, d0{24:8} selects the low byte of d0, and (a0){0:5} selects the highest five bits of the byte at a0.
A literal offset must be from 0 to 31, and a literal width from 1 to 32. Either can instead come from a data register, as in (a0){d1:d2}:
For a field in a data register, only the offset’s low five bits are used, giving a starting position from 0 to 31. A field that passes bit 0 wraps to bit 31 of the same register.
For a field in memory, a register offset is a signed 32-bit bit displacement. Positive offsets move forward through bytes, and negative offsets move backward. Offset -1 selects bit 0 of the preceding byte. A memory field continues into successive bytes without wrapping back to its starting byte.
A register-supplied width uses only the low five bits. Values 1 through 31 select that many bits, while zero selects 32. Thus a width register containing 32, 64 or zero selects 32 bits.
InstructionWhat it does with the field
bftstTests it, setting the flags
bfextu, bfextsCopies it into a data register, as an unsigned or a signed number
bfinsWrites the low bits of a data register into it
bfset, bfclr, bfchgSets, clears or inverts every bit of it
bfffoFinds its first 1
N copies the field’s highest bit, and Z is set if the field is zero. V and C are cleared, and X is unchanged. Instructions that change a field use its value before the change for N and Z. bfins uses the value being inserted instead.
Bit-field instructions are available with opt p=68020. opt bit also enables them in a 68000 or 68010 program, as in EASy68K, using that processor’s addressing modes. Since those processors have no hardware bit-field instructions, the editor uses 68020 timings and marks the program’s cycle count as an estimate.
This program extracts the red, green and blue components of a 16-bit colour:
    opt bit
    lea color, a0
    bfextu (a0){0:5}, d0      ; red, the first 5 bits: d0 = 31
    bfextu (a0){5:6}, d1      ; green, the next 6: d1 = 0
    bfextu (a0){11:5}, d2     ; blue, the last 5: d2 = 12
    simhalt

color:
    dc.w %1111100000001100

Instruction	What it does with the field
bftst	Tests it, setting the flags
bfextu, bfexts	Copies it into a data register, as an unsigned or a signed number
bfins	Writes the low bits of a data register into it
bfset, bfclr, bfchg	Sets, clears or inverts every bit of it
bfffo	Finds its first 1

Addressing modes