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divs

Signed divide

The default word form divides a signed 32-bit dividend by a signed 16-bit divisor.

Used in
XNZVC –??●0
  • ● depends on the result
  • 0 always 0
  • ? undefined (do not rely on it)
  • – not changed
  • After a division that does not overflow, N and Z describe the quotient.

Forms

68020 only

These forms require the 68020. Select opt p=68020 before any code or data.

Operands

<ea>
An operand using one of the addressing modes listed for this form. The list determines whether it can be a register, memory or an immediate value. With opt p=68020, an allowed d(An,Xn) or d(PC,Xn) mode also permits the corresponding 68020 indexed and memory indirect forms. See 68020 addressing. More
Dn
A data register, d0 to d7. More
Dr:Dq
A remainder register followed by a quotient register, for example d2:d1. For divs.l and divu.l, both supply the 64-bit dividend, high long first. For divsl.l and divul.l, only Dq supplies the 32-bit dividend. The quotient replaces Dq and the remainder replaces Dr. More
#imm
An immediate value written after #: a number, character or label, such as #10, #$FF or #'a'. It must fit the operation’s size: byte -128 to 255, word -32768 to 65535, or long -2147483648 to 4294967295; signed and unsigned spellings are accepted. More

The destination data register supplies the dividend. The source supplies the divisor. The quotient replaces the destination’s low word, and the remainder replaces its high word. The remainder has the dividend’s sign.

A zero divisor raises a division-by-zero exception through vector 5 at $14, leaving the destination unchanged. Without a handler, the program ends at divs. See writing a handler. A quotient outside the signed 16-bit range sets V and leaves the destination unchanged. Test V with bvs before using the result.

On the 68020, divs.l uses a 32-bit divisor. divs.l d0, d1 divides the 32-bit value in d1 by d0 and keeps only the quotient. divs.l d0, d2:d1 divides a 64-bit value, with its high long in d2 and low long in d1, by d0. It writes the quotient to d1 and the remainder to d2. A quotient too large for 32 bits sets V and leaves the registers unchanged. After a successful division, N and Z describe the quotient. Use different registers to keep both results. If both names refer to the same register, only the quotient remains.

divsl divides a 32-bit value and keeps the remainder too.

* --- Result: quotient in low word, remainder in high word ---
move.l #21, d0
divs #4, d0
move.w d0, d1 ; d1 = quotient (5)
swap d0
move.w d0, d2 ; d2 = remainder (1)

* --- Negative dividend ---
move.l #-21, d3
divs #4, d3
move.w d3, d4 ; d4 = quotient (-5)
swap d3
move.w d3, d5 ; d5 = remainder (-1)

; move.l #10, d6
; divs #0, d6 ; division by zero: with nothing at $14, the program ends here