MIPS Complete Documentation

ABSolute value : Set $t1 to absolute value of $t2 (algorithm from Hacker's Delight)

Floating-point absolute value (double) : Sets $f2 to the absolute value of $f4 (double-precision). Both register numbers must be even. Works by clearing the sign bit of the high word.

Floating-point absolute value (single) : Sets $f0 to the absolute value of $f1 (single-precision). Works by clearing the sign bit. Does not raise exceptions for NaN or infinity.

Add (signed, overflow trap) : Sets $t1 = $t2 + $t3 using signed 32-bit arithmetic. Raises an overflow exception if the true result does not fit in 32 bits. Use 'addu' when overflow should be silently ignored.

ADDition : set $t1 to ($t2 plus 16-bit immediate)

ADDition : set $t1 to ($t2 plus 32-bit immediate)

Floating-point add (double) : Sets $f2 = $f4 + $f6 using IEEE 754 double-precision (64-bit) arithmetic. Double-precision values have about 15 significant decimal digits. All three register numbers must be even, as each double occupies a pair of FP registers.

Floating-point add (single) : Sets $f0 = $f1 + $f3 using IEEE 754 single-precision (32-bit) arithmetic. Single-precision values have about 7 significant decimal digits. The result is stored in one FP register.

Add immediate (signed, overflow trap) : Sets $t1 = $t2 + immediate, where the immediate is a signed 16-bit constant (-32768 to 32767) sign-extended to 32 bits. Raises an overflow exception if the result overflows. Use 'addiu' to suppress the overflow check.

ADDition Immediate : set $t1 to ($t2 plus 32-bit immediate)

Add Lower Address : Set $t1 to $t2 plus the lower 16 bits of label's address

Add immediate unsigned (no overflow trap) : Sets $t1 = $t2 + immediate. The immediate is a signed 16-bit value sign-extended to 32 bits; no overflow exception is raised. Despite the name the immediate is sign-extended, not zero-extended. The most common add-immediate instruction.

ADDition Immediate Unsigned: set $t1 to ($t2 plus 32-bit immediate), no overflow

Add Lower Address : Set $t1 to $t2 plus the lower 16 bits of label's address

Add unsigned (no overflow trap) : Sets $t1 = $t2 + $t3. No exception is raised on overflow; the result wraps modulo 2^32. Despite the name, this works fine with signed values too when you don't need overflow detection.

ADDition Unsigned : set $t1 to ($t2 plus 32-bit immediate), no overflow

Bitwise AND : Sets $t1 = $t2 & $t3. Each bit of $t1 is 1 only if the corresponding bit is 1 in both $t2 and $t3. Commonly used to mask (isolate) specific bits in a value.

AND : set $t1 to ($t2 bitwise-AND 16-bit unsigned immediate)

AND : set $t1 to ($t1 bitwise-AND 16-bit unsigned immediate)

Bitwise AND immediate : Sets $t1 = $t2 & immediate. The 16-bit immediate is zero-extended (upper 16 bits become 0, not sign-extended) before the AND. Commonly used to mask off the lower 16 bits of a register or to test individual bits.

AND Immediate : set $t1 to ($t2 bitwise-AND 32-bit immediate)

AND Immediate : set $t1 to ($t1 bitwise-AND 16-bit unsigned immediate)

AND Immediate : set $t1 to ($t1 bitwise-AND 32-bit immediate)

Branch : Branch to statement at label unconditionally

Branch And Link : Branch to statement at label unconditionally, saving the return address in $ra. The counterpart of 'b' for calling a subroutine whose address is a label

Branch if FP condition flag 0 is false : Branches to 'label' if Coprocessor 1 condition flag 0 is false (0). Use after a FP compare instruction when you want to branch on the condition NOT being met. Note: mnemonic is BC1F, not BCLF.

Branch if specified FP condition flag is false : Branches to 'label' if the FP condition flag specified by the immediate operand is false (0). Allows branching on the unset result of any of the 8 FP condition flags.

Branch if FP condition flag 0 is true : Branches to 'label' if Coprocessor 1 condition flag 0 is true (1). Set by a preceding FP compare instruction such as 'c.eq.s' or 'c.lt.d'. Note: mnemonic is BC1T (branch Coprocessor-1 True), not BCLT.

Branch if specified FP condition flag is true : Branches to 'label' if the FP condition flag specified by the immediate operand is true (1). Allows branching on any of the 8 condition flags set by FP compare instructions.

Branch on equal : Branches to 'label' if $t1 == $t2. Uses a PC-relative 16-bit signed offset (multiplied by 4) so the target must be within ±32 KB. Commonly the first half of an if/else test.

Branch if EQual : Branch to statement at label if $t1 is equal to 16-bit immediate

Branch if EQual : Branch to statement at label if $t1 is equal to 32-bit immediate

Branch if EQual Zero : Branch to statement at label if $t1 is equal to zero

Branch if Greater or Equal : Branch to statement at label if $t1 is greater or equal to $t2

Branch if Greater or Equal : Branch to statement at label if $t1 is greater or equal to 16-bit immediate

Branch if Greater or Equal : Branch to statement at label if $t1 is greater or equal to 32-bit immediate

Branch if Greater or Equal Unsigned : Branch to statement at label if $t1 is greater or equal to $t2 (unsigned compare)

Branch if Greater or Equal Unsigned : Branch to statement at label if $t1 is greater or equal to 16-bit immediate (unsigned compare)

Branch if Greater or Equal Unsigned : Branch to statement at label if $t1 is greater or equal to 32-bit immediate (unsigned compare)

Branch on greater than or equal to zero : Branches to 'label' if $t1 >= 0 (signed comparison). Uses a PC-relative 16-bit signed offset. Commonly used to test the sign bit.

Branch on greater than or equal to zero and link : Branches to 'label' if $t1 >= 0 (signed), and saves the return address (PC + 4) in $ra. Combines a conditional branch with a function call. Use 'jr $ra' to return.

Branch if Greater Than : Branch to statement at label if $t1 is greater than $t2

Branch if Greater Than : Branch to statement at label if $t1 is greater than 16-bit immediate

Branch if Greater Than : Branch to statement at label if $t1 is greater than 32-bit immediate

Branch if Greater Than Unsigned: Branch to statement at label if $t1 is greater than $t2 (unsigned compare)

Branch if Greater Than Unsigned: Branch to statement at label if $t1 is greater than 16-bit immediate (unsigned compare)

Branch on greater than zero : Branches to 'label' if $t1 > 0 (signed comparison). Uses a PC-relative 16-bit signed offset.

Branch if Less or Equal : Branch to statement at label if $t1 is less than or equal to $t2

Branch if Less or Equal : Branch to statement at label if $t1 is less than or equal to 16-bit immediate

Branch if Less or Equal : Branch to statement at label if $t1 is less than or equal to 32-bit immediate

Branch if Less or Equal Unsigned : Branch to statement at label if $t1 is less than or equal to $t2 (unsigned compare)

Branch if Less or Equal Unsigned : Branch to statement at label if $t1 is less than or equal to 16-bit immediate (unsigned compare)

Branch if Less or Equal Unsigned : Branch to statement at label if $t1 is less than or equal to 32-bit immediate (unsigned compare)

Branch on less than or equal to zero : Branches to 'label' if $t1 <= 0 (signed comparison). Uses a PC-relative 16-bit signed offset.

Branch if Less Than : Branch to statement at label if $t1 is less than $t2

Branch if Less Than : Branch to statement at label if $t1 is less than 16-bit immediate

Branch if Less Than : Branch to statement at label if $t1 is less than 32-bit immediate

Branch if Less Than Unsigned : Branch to statement at label if $t1 is less than $t2

Branch if Less Than Unsigned : Branch to statement at label if $t1 is less than 16-bit immediate

Branch if Less Than Unsigned : Branch to statement at label if $t1 is less than 32-bit immediate

Branch on less than zero : Branches to 'label' if $t1 < 0 (signed comparison). Uses a PC-relative 16-bit signed offset.

Branch on less than zero and link : Branches to 'label' if $t1 < 0 (signed), and saves the return address (PC + 4) in $ra. Combines a conditional branch with a function call. Use 'jr $ra' to return.

Branch on not equal : Branches to 'label' if $t1 != $t2. Opposite of 'beq'. Uses a PC-relative 16-bit signed offset. Commonly used to branch out of loops or skip else blocks.

Branch if Not Equal : Branch to statement at label if $t1 is not equal to 16-bit immediate

Branch if Not Equal : Branch to statement at label if $t1 is not equal to 32-bit immediate

Branch if Not Equal Zero : Branch to statement at label if $t1 is not equal to zero

Breakpoint with code : Raises a breakpoint exception with the given numeric code. Halts execution in this simulator. Useful for embedding debug checkpoints in code, similar to a hardware breakpoint.

Breakpoint : Raises a breakpoint exception (no code). Halts execution in this simulator. Used as an unconditional software breakpoint — the zero-code variant of 'break N'.

FP compare eq (double) : Sets FP condition flag 0 to true if the two operands are equal, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare eq (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are equal, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare eq (single) : Sets FP condition flag 0 to true if the two operands are equal, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare eq (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are equal, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare f (double) : Sets FP condition flag 0 to true if never; this comparison is always false, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare f (double, flagged) : Sets FP condition flag N, named by the first operand, to true if never; this comparison is always false, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare f (single) : Sets FP condition flag 0 to true if never; this comparison is always false, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare f (single, flagged) : Sets FP condition flag N, named by the first operand, to true if never; this comparison is always false, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare le (double) : Sets FP condition flag 0 to true if the first operand is less than or equal to the second, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ole' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare le (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the first operand is less than or equal to the second, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ole' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare le (single) : Sets FP condition flag 0 to true if the first operand is less than or equal to the second, false otherwise. This is the signalling form, which behaves like 'c.ole' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare le (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the first operand is less than or equal to the second, false otherwise. This is the signalling form, which behaves like 'c.ole' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare lt (double) : Sets FP condition flag 0 to true if the first operand is less than the second, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.olt' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare lt (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the first operand is less than the second, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.olt' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare lt (single) : Sets FP condition flag 0 to true if the first operand is less than the second, false otherwise. This is the signalling form, which behaves like 'c.olt' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare lt (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the first operand is less than the second, false otherwise. This is the signalling form, which behaves like 'c.olt' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare nge (double) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than the second; the name reads as not greater than or equal, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ult' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare nge (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than the second; the name reads as not greater than or equal, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ult' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare nge (single) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than the second; the name reads as not greater than or equal, false otherwise. This is the signalling form, which behaves like 'c.ult' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare nge (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than the second; the name reads as not greater than or equal, false otherwise. This is the signalling form, which behaves like 'c.ult' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngl (double) : Sets FP condition flag 0 to true if the two operands are unordered or equal; the name reads as not greater than or less than, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ueq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngl (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered or equal; the name reads as not greater than or less than, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ueq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngl (single) : Sets FP condition flag 0 to true if the two operands are unordered or equal; the name reads as not greater than or less than, false otherwise. This is the signalling form, which behaves like 'c.ueq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngl (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered or equal; the name reads as not greater than or less than, false otherwise. This is the signalling form, which behaves like 'c.ueq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngle (double) : Sets FP condition flag 0 to true if the two operands are unordered; the name reads as not greater than, less than or equal, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.un' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngle (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered; the name reads as not greater than, less than or equal, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.un' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngle (single) : Sets FP condition flag 0 to true if the two operands are unordered; the name reads as not greater than, less than or equal, false otherwise. This is the signalling form, which behaves like 'c.un' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngle (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered; the name reads as not greater than, less than or equal, false otherwise. This is the signalling form, which behaves like 'c.un' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngt (double) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than or equal to the second; the name reads as not greater than, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ule' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngt (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than or equal to the second; the name reads as not greater than, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.ule' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngt (single) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than or equal to the second; the name reads as not greater than, false otherwise. This is the signalling form, which behaves like 'c.ule' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ngt (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than or equal to the second; the name reads as not greater than, false otherwise. This is the signalling form, which behaves like 'c.ule' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ole (double) : Sets FP condition flag 0 to true if both operands are ordered and the first is less than or equal to the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ole (double, flagged) : Sets FP condition flag N, named by the first operand, to true if both operands are ordered and the first is less than or equal to the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ole (single) : Sets FP condition flag 0 to true if both operands are ordered and the first is less than or equal to the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ole (single, flagged) : Sets FP condition flag N, named by the first operand, to true if both operands are ordered and the first is less than or equal to the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare olt (double) : Sets FP condition flag 0 to true if both operands are ordered and the first is less than the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare olt (double, flagged) : Sets FP condition flag N, named by the first operand, to true if both operands are ordered and the first is less than the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare olt (single) : Sets FP condition flag 0 to true if both operands are ordered and the first is less than the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare olt (single, flagged) : Sets FP condition flag N, named by the first operand, to true if both operands are ordered and the first is less than the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare seq (double) : Sets FP condition flag 0 to true if the two operands are equal, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.eq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare seq (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are equal, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.eq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare seq (single) : Sets FP condition flag 0 to true if the two operands are equal, false otherwise. This is the signalling form, which behaves like 'c.eq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare seq (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are equal, false otherwise. This is the signalling form, which behaves like 'c.eq' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare sf (double) : Sets FP condition flag 0 to true if never; this comparison is always false, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.f' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare sf (double, flagged) : Sets FP condition flag N, named by the first operand, to true if never; this comparison is always false, false otherwise. Both register numbers must be even. This is the signalling form, which behaves like 'c.f' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare sf (single) : Sets FP condition flag 0 to true if never; this comparison is always false, false otherwise. This is the signalling form, which behaves like 'c.f' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare sf (single, flagged) : Sets FP condition flag N, named by the first operand, to true if never; this comparison is always false, false otherwise. This is the signalling form, which behaves like 'c.f' here because FP exceptions are not tracked. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ueq (double) : Sets FP condition flag 0 to true if the two operands are unordered or equal, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ueq (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered or equal, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ueq (single) : Sets FP condition flag 0 to true if the two operands are unordered or equal, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ueq (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered or equal, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ule (double) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than or equal to the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ule (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than or equal to the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ule (single) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than or equal to the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ule (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than or equal to the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ult (double) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ult (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than the second, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ult (single) : Sets FP condition flag 0 to true if the two operands are unordered, or the first is less than the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare ult (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, or the first is less than the second, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare un (double) : Sets FP condition flag 0 to true if the two operands are unordered, which is the case when either one is NaN, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare un (double, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, which is the case when either one is NaN, false otherwise. Both register numbers must be even. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare un (single) : Sets FP condition flag 0 to true if the two operands are unordered, which is the case when either one is NaN, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

FP compare un (single, flagged) : Sets FP condition flag N, named by the first operand, to true if the two operands are unordered, which is the case when either one is NaN, false otherwise. Use 'bc1t' or 'bc1f' to branch on the result.

Ceiling double-precision to word : Converts the double-precision float in $f2 (even-numbered register) to a 32-bit integer by rounding toward positive infinity, storing the result in $f1.

Ceiling single-precision to word : Converts the single-precision float in $f1 to a 32-bit integer by rounding toward positive infinity, and stores the result in $f0.

Move control word from FPU : Copies an FPU control register into integer register $t1. Register 31 is FCSR and register 25 is FCCR, both of which report the condition codes set by the 'c.eq.s', 'c.lt.s' family. Only the condition codes are modelled here; the rounding mode and exception fields read as 0.

Count leading ones : Sets $t1 to the number of consecutive 1 bits in $t2, counted from the most-significant bit downward. For example, if $t2 = 0b11100000..., then $t1 = 3. Returns 32 if all bits are 1.

Count leading zeros : Sets $t1 to the number of consecutive 0 bits in $t2, counted from the most-significant bit downward. For example, if $t2 = 0b00010000..., then $t1 = 3. Returns 32 if $t2 is 0. Often used to compute floor(log2(n)) or to normalize values.

Move control word to FPU : Copies integer register $t1 into an FPU control register. Register 31 is FCSR and register 25 is FCCR. Only the condition code bits take effect; the rounding mode and exception fields are ignored because this simulator always rounds to nearest and does not track FP exceptions.

Convert single-precision to double-precision : Converts the single-precision float in $f1 to double-precision (64-bit IEEE 754) and stores the result in $f2. $f2 must be even-numbered. No data is lost because double has more precision.

Convert integer word to double-precision : Treats the 32-bit integer stored in $f1 as a signed integer and converts it to a double-precision float stored in $f2. $f2 must be even-numbered.

Convert double-precision to single-precision : Converts the double-precision float in $f2 to single-precision and stores the result in $f1. $f2 must be even-numbered. Precision may be lost since single has fewer significant digits.

Convert integer word to single-precision : Treats the 32-bit integer stored in $f1 as a signed integer and converts it to a single-precision float stored in $f0.

Convert double-precision to integer word : Converts the double-precision float in $f2 to a signed 32-bit integer by truncation and stores the result in $f1. $f2 must be even-numbered. Use 'mfc1' to move the integer result to a general-purpose register.

Convert single-precision to integer word : Converts the single-precision float in $f1 to a signed 32-bit integer by truncation and stores the result in $f0. Use 'mfc1' to move the integer result to a general-purpose register.

Divide signed : Divides $t1 by $t2 (signed). Sets LO to the quotient and HI to the remainder. Division by zero produces undefined results with no exception. Use 'mflo' to get the quotient; 'mfhi' to get the remainder.

DIVision : Set $t1 to ($t2 divided by $t3, integer division)

DIVision : Set $t1 to ($t2 divided by 16-bit immediate, integer division)

DIVision : Set $t1 to ($t2 divided by 32-bit immediate, integer division)

Floating-point divide (double) : Sets $f2 = $f4 / $f6 using IEEE 754 double-precision (64-bit) arithmetic. All register numbers must be even.

Floating-point divide (single) : Sets $f0 = $f1 / $f3 using IEEE 754 single-precision (32-bit) arithmetic. Dividing by zero produces +/-Infinity according to IEEE 754.

Divide unsigned : Divides $t1 by $t2 treating both as unsigned 32-bit integers. Sets LO to the quotient and HI to the remainder. Division by zero produces undefined results with no exception. Use 'mflo' for the quotient; 'mfhi' for the remainder.

DIVision Unsigned : Set $t1 to ($t2 divided by $t3, unsigned integer division)

DIVision Unsigned : Set $t1 to ($t2 divided by 16-bit immediate, unsigned integer division)

DIVision Unsigned : Set $t1 to ($t2 divided by 32-bit immediate, unsigned integer division)

Exception return : Returns from an exception or interrupt handler. Restores the PC from the EPC register (Coprocessor 0 register 14) and clears the Exception Level bit (bit 1) in the Status register, re-enabling interrupts and returning to user mode.

Floor double-precision to word : Converts the double-precision float in $f2 (even-numbered register) to a 32-bit integer by rounding toward negative infinity, storing the result in $f1.

Floor single-precision to word : Converts the single-precision float in $f1 to a 32-bit integer by rounding toward negative infinity (i.e., always truncates toward -inf), and stores the result in $f0. Use 'mfc1' to move the result to a general-purpose register.

Jump unconditionally : Transfers execution to 'target'. The destination is encoded as a 26-bit word address; the upper 4 bits of PC are combined with this value, so the target must be in the same 256 MB region as the instruction following the jump.

Jump and link : Saves the return address (PC + 4) in $ra, then jumps to 'target'. The standard function-call instruction in MIPS. The called function returns with 'jr $ra'. Same address-range restriction as 'j'.

Jump and link register : Saves the return address (PC + 4) in $t1, then jumps to the address in $t2. Allows calling a function whose address is only known at runtime (function pointer). Return with 'jr $t1'.

Jump and link register : Saves the return address (PC + 4) in $ra, then jumps to the address in $t1. One-operand shorthand for 'jalr $ra,$t1'. Used to call a function via a pointer stored in a register.

Jump register : Transfers execution to the address stored in $t1. Most commonly used as 'jr $ra' to return from a function call made with 'jal' or 'jalr'.

Load floating point Double precision : Set $f2 and $f3 register pair to 64-bit value at effective memory doubleword address

Load floating point Single precision : Set $f1 to 32-bit value at effective memory word address

Load Address : Set $t1 to contents of $t2

Load Address : Set $t1 to 16-bit immediate (sign-extended)

Load Address : Set $t1 to 16-bit immediate (zero-extended)

Load Address : Set $t1 to 32-bit immediate

Load Address : Set $t1 to sum (of $t2 and 16-bit immediate)

Load Address : Set $t1 to sum (of $t2 and 32-bit immediate)

Load Address : Set $t1 to label's address

Load Address : Set $t1 to sum (of $t2 and label's address)

Load Address : Set $t1 to sum (of label's address and 32-bit immediate)

Load Address : Set $t1 to sum (of label's address, 32-bit immediate, and $t2)

Load byte (sign-extended) : Reads one byte from memory at address ($t2 + offset), sign-extends it to 32 bits, and stores the result in $t1. A byte with value 0xFF becomes -1 (0xFFFFFFFF) in $t1. Use 'lbu' if you want zero-extension (0 to 255 range).

Load from Address : Read from label's address, reached through the %hi already in $t2

Load Byte : Set $t1 to sign-extended 8-bit value from effective memory byte address

Load byte unsigned (zero-extended) : Reads one byte from memory at address ($t2 + offset), zero-extends it to 32 bits (upper 24 bits of $t1 are always 0), and stores the result in $t1. Values range from 0 to 255. Use 'lb' if you need sign-extension.

Load from Address : Read from label's address, reached through the %hi already in $t2

Load Byte Unsigned : Set $t1 to zero-extended 8-bit value from effective memory byte address

Load Doubleword : Set $t1 and the next register to the 64 bits starting at effective memory byte address

Load Doubleword : Set $t1 and the next register to the 64 bits starting at effective memory word address

Load doubleword to FP register pair : Loads a 64-bit value from memory at address ($t2 + offset) into the even FP register pair $f2/$f3. Used to load a double-precision float from memory. Address must be doubleword-aligned and $f2 must be even-numbered.

Load from Address : Read from label's address, reached through the %hi already in $t2

Load Doubleword Coprocessor 1 : Set $f2 and $f3 register pair to 64-bit value at effective memory doubleword address

Load halfword (sign-extended) : Reads a 16-bit value from memory at address ($t2 + offset), sign-extends it to 32 bits, and stores the result in $t1. The address must be halfword-aligned (divisible by 2). Use 'lhu' for zero-extension.

Load from Address : Read from label's address, reached through the %hi already in $t2

Load Halfword : Set $t1 to sign-extended 16-bit value from effective memory halfword address

Load halfword unsigned (zero-extended) : Reads a 16-bit value from memory at address ($t2 + offset), zero-extends it to 32 bits (upper 16 bits of $t1 are always 0), and stores the result in $t1. The address must be halfword-aligned (divisible by 2).

Load from Address : Read from label's address, reached through the %hi already in $t2

Load Halfword Unsigned : Set $t1 to zero-extended 16-bit value from effective memory halfword address

Load Immediate : Set $t1 to 16-bit immediate (sign-extended)

Load Immediate : Set $t1 to unsigned 16-bit immediate (zero-extended)

Load Immediate : Set $t1 to 32-bit immediate

Load linked : Identical to 'lw' in this simulator (reads 32 bits from memory into $t1). In real multi-processor hardware, 'll' is the first half of an atomic read-modify-write pair with 'sc' (store conditional), allowing lock-free synchronization.

Load Linked : Paired with Store Conditional (sc) to perform atomic read-modify-write. Treated as equivalent to Load Word (lw) because MARS does not simulate multiple processors.

Load upper immediate : Places the 16-bit immediate into the upper 16 bits of $t1 and clears the lower 16 bits to 0. Used to build a full 32-bit constant: first 'lui $t1,upper16' then 'ori $t1,$t1,lower16'. Example: to load 0x12345678 use 'lui $t1,0x1234' then 'ori $t1,$t1,0x5678'.

Load Upper Address : Set $t1 to the upper 16 bits of label's address, adjusted so that a following %lo lands on the label. Pairs with an instruction taking %lo(label)($t1)

Load word : Reads the 32-bit (4-byte) value at memory address ($t2 + offset) and places it in $t1. The address must be word-aligned (divisible by 4). Example: 'lw $t0,0($sp)' loads the value at the top of the stack.

Load Word : Set $t1 to contents of effective memory word address

Load Word : Set $t1 to contents of memory word at label's address

Load from Address : Read from label's address, reached through the %hi already in $t2

Load Word : Set $t1 to contents of effective memory word address

Load word to FP register : Loads a 32-bit value from memory at address ($t2 + offset) directly into FP register $f1. Typically used to load a single-precision float from memory. Address must be word-aligned.

Load from Address : Read from label's address, reached through the %hi already in $t2

Load Word Coprocessor 1 : Set $f1 to 32-bit value from effective memory word address

Load word left (unaligned) : Loads 1-4 bytes into the most-significant (left) bytes of $t1 starting from the effective byte address and working toward the low byte of the containing word. Use together with 'lwr' to load a full 32-bit word from an unaligned address.

Load Word Left : Load from 1 to 4 bytes left-justified into $t1, starting with effective memory byte address and continuing through the low-order byte of its word

Load word right (unaligned) : Loads 1-4 bytes into the least-significant (right) bytes of $t1 starting from the effective byte address and working toward the high byte of the containing word. Use together with 'lwl' to load a full 32-bit word from an unaligned address.

Load Word Right : Load from 1 to 4 bytes right-justified into $t1, starting with effective memory byte address and continuing through the high-order byte of its word

Multiply-accumulate signed : Multiplies $t1 by $t2 (signed) to form a 64-bit product, then adds that product to the current 64-bit value in HI:LO. Useful for computing dot-products or sums of products without extra move instructions.

Multiply-accumulate unsigned : Multiplies $t1 by $t2 treating both as unsigned 32-bit integers, then adds the 64-bit product to HI:LO. Use 'mfhi'/'mflo' to read the accumulated result.

Move from Coprocessor 0 : Reads a Coprocessor 0 (CP0) control register and places its value in general-purpose register $t1. CP0 registers hold exception/interrupt state: register 8 (BadVAddr), 12 (Status), 13 (Cause), 14 (EPC), etc.

Move from FP register to integer register : Copies the raw 32-bit bit-pattern stored in FP register $f1 into integer register $t1. Useful for reading a single-precision float's bits or the result of 'floor.w.s', 'cvt.w.s', etc.

Move From Coprocessor 1 Double : Set $t1 to contents of $f2, set next higher register from $t1 to contents of next higher register from $f2

Move from HI : Copies the special HI register into $t1. HI holds the upper 32 bits of a multiply result or the remainder from a divide. Always read HI/LO before executing another multiply or divide, as those instructions overwrite them.

Move from LO : Copies the special LO register into $t1. LO holds the lower 32 bits of a multiply result or the quotient from a divide. Always read HI/LO before executing another multiply or divide, as those instructions overwrite them.

Move double-precision FP register : Copies the double-precision value in $f4 into $f2. Both register numbers must be even. Does not perform any conversion.

Move single-precision FP register : Copies the single-precision value in $f1 into $f0. Does not perform any conversion.

MOVE : Set $t1 to contents of $t2

Move if FP condition flag 0 is false : Copies $t2 into $t1 if floating-point condition flag 0 is false (0). Allows integer register updates to be conditioned on the result of a previous FP comparison (e.g., c.eq.s, c.lt.s).

Move if specified FP condition flag is false : Copies $t2 into $t1 if FP condition flag N (specified by the third operand) is false (0). Allows results of multiple simultaneous FP comparisons to control integer register moves.

Move double-precision FP if condition flag 0 is false : Copies the double-precision value in $f4 into $f2 if FP condition flag 0 is false (0). Both register numbers must be even.

Move double-precision FP if specified condition flag is false : Copies the double-precision value in $f4 into $f2 if FP condition flag N (specified by the immediate) is false (0). Both register numbers must be even.

Move single-precision FP if condition flag 0 is false : Copies the single-precision value in $f1 into $f0 if FP condition flag 0 is false (0).

Move single-precision FP if specified condition flag is false : Copies the single-precision value in $f1 into $f0 if FP condition flag N (specified by the immediate) is false (0).

Move if not zero : Copies $t2 into $t1 only if $t3 != 0. Allows branchless conditional assignment — avoids a branch instruction when you only need to update a register conditionally.

Move double-precision FP if integer register not zero : Copies the double-precision value in $f4 into $f2 if $t3 != 0. Both FP register numbers must be even.

Move single-precision FP if integer register not zero : Copies the single-precision value in $f1 into $f0 if $t3 != 0.

Move if FP condition flag 0 is true : Copies $t2 into $t1 if floating-point condition flag 0 is true (1). Allows integer register updates to be conditioned on the result of a previous FP comparison (e.g., c.eq.s, c.lt.s).

Move if specified FP condition flag is true : Copies $t2 into $t1 if FP condition flag N (specified by the third operand) is true (1). Allows results of multiple simultaneous FP comparisons to control integer register moves.

Move double-precision FP if condition flag 0 is true : Copies the double-precision value in $f4 into $f2 if FP condition flag 0 is true (1). Both register numbers must be even.

Move double-precision FP if specified condition flag is true : Copies the double-precision value in $f4 into $f2 if FP condition flag N (specified by the immediate) is true (1). Both register numbers must be even.

Move single-precision FP if condition flag 0 is true : Copies the single-precision value in $f1 into $f0 if FP condition flag 0 is true (1).

Move single-precision FP if specified condition flag is true : Copies the single-precision value in $f1 into $f0 if FP condition flag N (specified by the immediate) is true (1).

Move if zero : Copies $t2 into $t1 only if $t3 == 0. Allows branchless conditional assignment — avoids a branch instruction when you only need to update a register conditionally.

Move double-precision FP if integer register is zero : Copies the double-precision value in $f4 into $f2 if $t3 == 0. Both FP register numbers must be even.

Move single-precision FP if integer register is zero : Copies the single-precision value in $f1 into $f0 if $t3 == 0.

Multiply-subtract signed : Multiplies $t1 by $t2 (signed) to form a 64-bit product, then subtracts that product from the current 64-bit value in HI:LO. Use 'mfhi'/'mflo' to read the result.

Multiply-subtract unsigned : Multiplies $t1 by $t2 treating both as unsigned 32-bit integers, then subtracts the 64-bit product from HI:LO. Use 'mfhi'/'mflo' to read the result.

Move to Coprocessor 0 : Writes the value of general-purpose register $t1 into a Coprocessor 0 (CP0) control register. Used by exception handlers to modify the Status and Cause registers or to clear the EPC.

Move from integer register to FP register : Copies the 32-bit value in integer register $t1 into FP register $f1 without any conversion. Useful for initializing a FP register with a specific bit pattern or loading a freshly-computed integer before 'cvt.s.w'.

Move To Coprocessor 1 Double : Set $f2 to contents of $t1, set next higher register from $f2 to contents of next higher register from $t1

Move to HI : Copies $t1 into the special HI register, overwriting any prior multiply or divide result stored there.

Move to LO : Copies $t1 into the special LO register, overwriting any prior multiply or divide result stored there.

Multiply (low 32-bit result to register) : Multiplies $t2 by $t3 (signed) and stores the lower 32 bits of the product directly into $t1 and also into LO. No overflow exception is raised. HI is updated with the upper 32 bits.

MULtiplication : Set HI to high-order 32 bits, LO and $t1 to low-order 32 bits of the product of $t2 and 16-bit signed immediate (use mfhi to access HI, mflo to access LO)

MULtiplication : Set HI to high-order 32 bits, LO and $t1 to low-order 32 bits of the product of $t2 and 32-bit immediate (use mfhi to access HI, mflo to access LO)

Floating-point multiply (double) : Sets $f2 = $f4 * $f6 using IEEE 754 double-precision (64-bit) arithmetic. All register numbers must be even.

Floating-point multiply (single) : Sets $f0 = $f1 * $f3 using IEEE 754 single-precision (32-bit) arithmetic.

MULtiplication with Overflow : Set $t1 to low-order 32 bits of the product of $t2 and $t3

MULtiplication with Overflow : Set $t1 to low-order 32 bits of the product of $t2 and signed 16-bit immediate

MULtiplication with Overflow : Set $t1 to low-order 32 bits of the product of $t2 and 32-bit immediate

MULtiplication with Overflow Unsigned : Set $t1 to low-order 32 bits of the product of $t2 and $t3

MULtiplication with Overflow Unsigned : Set $t1 to low-order 32 bits of the product of $t2 and signed 16-bit immediate

MULtiplication with Overflow Unsigned : Set $t1 to low-order 32 bits of the product of $t2 and 32-bit immediate

Multiply signed : Multiplies $t1 by $t2 as signed 32-bit integers. The 64-bit product is split: the upper 32 bits go into the HI register and the lower 32 bits go into the LO register. Use 'mfhi' to read HI and 'mflo' to read LO.

Multiply unsigned : Multiplies $t1 by $t2 treating both as unsigned 32-bit integers. The 64-bit product is split: upper 32 bits go into HI, lower 32 bits go into LO. Use 'mfhi'/'mflo' to retrieve the results.

MULtiplication Unsigned : Set HI to high-order 32 bits, LO and $t1 to low-order 32 bits of ($t2 multiplied by $t3, unsigned multiplication)

MULtiplication Unsigned : Set HI to high-order 32 bits, LO and $t1 to low-order 32 bits of ($t2 multiplied by 16-bit immediate, unsigned multiplication)

MULtiplication Unsigned : Set HI to high-order 32 bits, LO and $t1 to low-order 32 bits of ($t2 multiplied by 32-bit immediate, unsigned multiplication)

NEGate : Set $t1 to negation of $t2

Floating-point negate (double) : Sets $f2 to the negation of $f4 (double-precision) by flipping the sign bit. Both register numbers must be even.

Floating-point negate (single) : Sets $f0 to the negation of $f1 (single-precision) by flipping the sign bit.

NEGate Unsigned : Set $t1 to negation of $t2, no overflow

No operation : Does nothing; the processor simply advances to the next instruction. Machine code is all zeroes. Useful as a placeholder or delay-slot filler.

Bitwise NOR : Sets $t1 = ~($t2 | $t3). Each bit of $t1 is 1 only if the corresponding bit is 0 in both $t2 and $t3. Tip: 'nor $t1,$t2,$zero' computes a bitwise NOT of $t2, since MIPS has no dedicated NOT instruction.

Bitwise NOT (bit inversion)

Bitwise OR : Sets $t1 = $t2 | $t3. Each bit of $t1 is 1 if the corresponding bit is 1 in either $t2 or $t3 (or both). Commonly used to set specific bits in a value.

OR : set $t1 to ($t2 bitwise-OR 16-bit unsigned immediate)

OR : set $t1 to ($t1 bitwise-OR 16-bit unsigned immediate)

Bitwise OR immediate : Sets $t1 = $t2 | immediate. The 16-bit immediate is zero-extended before the OR. Commonly used to set specific bits or to load a small non-negative constant into a register (e.g. after 'lui').

OR Immediate : set $t1 to ($t2 bitwise-OR 32-bit immediate)

OR Immediate : set $t1 to ($t1 bitwise-OR 16-bit unsigned immediate)

OR Immediate : set $t1 to ($t1 bitwise-OR 32-bit immediate)

Or Lower Address : Set $t1 to $t2 or the lower 16 bits of label's address

Prefetch : Hints that the data at address ($t2 + offset) will be needed soon, so the hardware can begin moving it into cache. The first operand is the hint type. A prefetch is only ever a hint and never changes what a program computes; this simulator has no cache, so it does nothing. It is accepted so that compiler output assembles unchanged.

REMainder : Set $t1 to (remainder of $t2 divided by $t3)

REMainder : Set $t1 to (remainder of $t2 divided by 16-bit immediate)

REMainder : Set $t1 to (remainder of $t2 divided by 32-bit immediate)

REMainder : Set $t1 to (remainder of $t2 divided by $t3, unsigned division)

REMainder : Set $t1 to (remainder of $t2 divided by 16-bit immediate, unsigned division)

REMainder : Set $t1 to (remainder of $t2 divided by 32-bit immediate, unsigned division)

ROtate Left : Set $t1 to ($t2 rotated left by number of bit positions specified in $t3)

ROtate Left : Set $t1 to ($t2 rotated left by number of bit positions specified in 5-bit immediate)

ROtate Right : Set $t1 to ($t2 rotated right by number of bit positions specified in $t3)

ROtate Right : Set $t1 to ($t2 rotated right by number of bit positions specified in 5-bit immediate)

Rotate right : Sets $t1 = $t2 rotated right by immediate (0-31 bits). Unlike 'srl', bits shifted off the right re-enter on the left rather than being discarded, so no information is lost. Encoded as 'srl' with bit 21 set.

Rotate right variable : Sets $t1 = $t2 rotated right by ($t3 & 31). Like 'rotr' but the rotate amount comes from the lowest 5 bits of register $t3 rather than an immediate constant.

Round double-precision to word : Converts the double-precision float in $f2 (even-numbered register) to the nearest 32-bit integer (round half to even, per IEEE 754), storing the result in $f1.

Round single-precision to word : Converts the single-precision float in $f1 to the nearest 32-bit integer (round half to even, per IEEE 754), and stores the result in $f0.

Store floating point Double precision : Store 64 bits from $f2 and $f3 register pair to effective memory doubleword address

Store floating point Single precision : Store 32-bit value from $f1 to effective memory word address

Store byte : Writes the lowest 8 bits of $t1 to memory at address ($t2 + offset). The upper 24 bits of $t1 are ignored. Useful for writing single characters or packed byte arrays.

Store to Address : Write to label's address, reached through the %hi already in $t2

Store Byte : Store the low-order 8 bits of $t1 into the effective memory byte address

Store conditional : Stores the value of $t1 into memory at address ($t2 + offset), then sets $t1 = 1 (success). In real multi-processor hardware this can fail (setting $t1 = 0) if another processor modified the target location since the preceding 'll'. Always succeeds in this simulator.

Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors.

Store Doubleword : Store contents of $t1 and the next register to the 64 bits starting at effective memory byte address

Store Doubleword : Store contents of $t1 and the next register to the 64 bits starting at effective memory word address

Store doubleword from FP register pair : Writes the 64-bit value in the even FP register pair $f2/$f3 to memory at address ($t2 + offset). Used to store a double-precision float to memory. Address must be doubleword-aligned and $f2 must be even-numbered.

Store to Address : Write to label's address, reached through the %hi already in $t2

Store Doubleword Coprocessor 1 : Store 64 bits from $f2 and $f3 register pair to effective memory doubleword address

Sign extend byte : Copies the low 8 bits of $t2 into $t1, with bit 7 replicated through the upper 24 bits. Turns a byte loaded with 'lbu', or one extracted by shifting, back into a signed value.

Sign extend halfword : Copies the low 16 bits of $t2 into $t1, with bit 15 replicated through the upper 16 bits. Turns a halfword loaded with 'lhu' back into a signed value.

Set EQual : if $t2 equal to $t3 then set $t1 to 1 else 0

Set EQual : if $t2 equal to 16-bit immediate then set $t1 to 1 else 0

Set EQual : if $t2 equal to 32-bit immediate then set $t1 to 1 else 0

Set Greater or Equal : if $t2 greater or equal to $t3 then set $t1 to 1 else 0

Set Greater or Equal : if $t2 greater or equal to 16-bit immediate then set $t1 to 1 else 0

Set Greater or Equal : if $t2 greater or equal to 32-bit immediate then set $t1 to 1 else 0

Set Greater or Equal Unsigned : if $t2 greater or equal to $t3 (unsigned compare) then set $t1 to 1 else 0

Set Greater or Equal Unsigned : if $t2 greater or equal to 16-bit immediate (unsigned compare) then set $t1 to 1 else 0

Set Greater or Equal Unsigned : if $t2 greater or equal to 32-bit immediate (unsigned compare) then set $t1 to 1 else 0

Set Greater Than : if $t2 greater than $t3 then set $t1 to 1 else 0

Set Greater Than : if $t2 greater than 16-bit immediate then set $t1 to 1 else 0

Set Greater Than : if $t2 greater than 32-bit immediate then set $t1 to 1 else 0

Set Greater Than Unsigned : if $t2 greater than $t3 (unsigned compare) then set $t1 to 1 else 0

Set Greater Than Unsigned : if $t2 greater than 16-bit immediate (unsigned compare) then set $t1 to 1 else 0

Set Greater Than Unsigned : if $t2 greater than 32-bit immediate (unsigned compare) then set $t1 to 1 else 0

Store halfword : Writes the lowest 16 bits of $t1 to memory at address ($t2 + offset). The upper 16 bits of $t1 are ignored. The address must be halfword-aligned (divisible by 2).

Store to Address : Write to label's address, reached through the %hi already in $t2

Store Halfword : Store the low-order 16 bits of $t1 into the effective memory halfword address

Set Less or Equal : if $t2 less or equal to $t3 then set $t1 to 1 else 0

Set Less or Equal : if $t2 less or equal to 16-bit immediate then set $t1 to 1 else 0

Set Less or Equal : if $t2 less or equal to 32-bit immediate then set $t1 to 1 else 0

Set Less or Equal Unsigned: if $t2 less or equal to $t3 (unsigned compare) then set $t1 to 1 else 0

Set Less or Equal Unsigned: if $t2 less or equal to 16-bit immediate (unsigned compare) then set $t1 to 1 else 0

Set Less or Equal Unsigned: if $t2 less or equal to 32-bit immediate (unsigned compare) then set $t1 to 1 else 0

Shift left logical : Sets $t1 = $t2 << immediate (0-31 bits). Vacated bits on the right are filled with 0. Shifting left by n is equivalent to multiplying by 2^n (without overflow checking). Example: sll $t1,$t1,2 multiplies $t1 by 4.

Shift left logical variable : Sets $t1 = $t2 << ($t3 & 31). Like 'sll' but the shift amount is taken from the lowest 5 bits of register $t3 rather than an immediate constant. The upper 27 bits of $t3 are ignored.

Set on less than (signed) : Sets $t1 = 1 if $t2 < $t3 (signed comparison), otherwise $t1 = 0. Useful for conditional logic without branches. Pair with 'bne $t1,$zero,label' or 'beq $t1,$zero,label' to branch on the result.

Set on less than immediate (signed) : Sets $t1 = 1 if $t2 < immediate (sign-extended to 32 bits), otherwise $t1 = 0. Convenient for loop bounds and range checking without a separate load instruction.

Set on less than immediate unsigned : Sets $t1 = 1 if $t2 < immediate using unsigned comparison. The immediate is sign-extended to 32 bits first, then interpreted as unsigned. Commonly used to test if a value is below a limit without needing a separate register.

Set on less than unsigned : Sets $t1 = 1 if $t2 < $t3 using unsigned comparison, otherwise $t1 = 0. Treats both operands as unsigned 32-bit integers (0 to 4294967295). Use this when comparing memory addresses or unsigned counters.

Set Not Equal : if $t2 not equal to $t3 then set $t1 to 1 else 0

Set Not Equal : if $t2 not equal to 16-bit immediate then set $t1 to 1 else 0

Set Not Equal : if $t2 not equal to 32-bit immediate then set $t1 to 1 else 0

Floating-point square root (double) : Sets $f2 = sqrt($f4) using double-precision arithmetic. Both register numbers must be even. Returns NaN if $f4 is negative.

Floating-point square root (single) : Sets $f0 = sqrt($f1) using single-precision arithmetic. Returns NaN if $f1 is negative.

Shift right arithmetic : Sets $t1 = $t2 >> immediate (0-31 bits). Vacated bits on the left are filled with copies of the sign bit, preserving the sign of negative numbers. Shifting right by n is equivalent to signed division by 2^n rounding toward negative infinity.

Shift right arithmetic variable : Sets $t1 = $t2 >> ($t3 & 31). Like 'sra' but the shift amount is taken from the lowest 5 bits of register $t3. Vacated bits are sign-filled.

Shift right logical : Sets $t1 = $t2 >>> immediate (0-31 bits). Vacated bits on the left are filled with 0 (unsigned shift). Shifting right by n is equivalent to unsigned division by 2^n. Use 'sra' to preserve the sign bit instead.

Shift right logical variable : Sets $t1 = $t2 >>> ($t3 & 31). Like 'srl' but the shift amount is taken from the lowest 5 bits of register $t3 rather than an immediate constant. Vacated bits are zero-filled.

Subtract (signed, overflow trap) : Sets $t1 = $t2 - $t3 using signed 32-bit arithmetic. Raises an overflow exception if the true result does not fit in 32 bits. Use 'subu' when overflow should be silently ignored.

SUBtraction : set $t1 to ($t2 minus 16-bit immediate)

SUBtraction : set $t1 to ($t2 minus 32-bit immediate)

Floating-point subtract (double) : Sets $f2 = $f4 - $f6 using IEEE 754 double-precision (64-bit) arithmetic. All register numbers must be even.

Floating-point subtract (single) : Sets $f0 = $f1 - $f3 using IEEE 754 single-precision (32-bit) arithmetic.

SUBtraction Immediate : set $t1 to ($t2 minus 16-bit immediate)

SUBtraction Immediate : set $t1 to ($t2 minus 32-bit immediate)

SUBtraction Immediate Unsigned : set $t1 to ($t2 minus 32-bit immediate), no overflow

Subtract unsigned (no overflow trap) : Sets $t1 = $t2 - $t3. No exception is raised on overflow; the result wraps modulo 2^32. The most common subtract instruction in practice.

SUBtraction Unsigned : set $t1 to ($t2 minus 32-bit immediate), no overflow

Store word : Writes the 32-bit value in $t1 to memory at address ($t2 + offset). The address must be word-aligned (divisible by 4). Example: 'sw $t0,0($sp)' stores a value at the top of the stack.

Store to Address : Write to label's address, reached through the %hi already in $t2

Store Word : Store $t1 contents into effective memory word address

Store Word : Store $t1 contents into memory word at label's address

Store word from FP register : Writes the 32-bit value in FP register $f1 to memory at address ($t2 + offset). Typically used to store a single-precision float to memory. Address must be word-aligned.

Store to Address : Write to label's address, reached through the %hi already in $t2

Store Word Coprocessor 1 : Store 32-bit value from $f1 to effective memory word address

Store word left (unaligned) : Writes 1-4 bytes from the most-significant (left) bytes of $t1 into memory starting at the effective byte address and working toward the low byte of the containing aligned word. Use together with 'swr' to store a full word at an unaligned address.

Store Word Left : Store high-order 1 to 4 bytes of $t1 into memory, starting with effective memory byte address and continuing through the low-order byte of its word

Store word right (unaligned) : Writes 1-4 bytes from the least-significant (right) bytes of $t1 into memory starting at the high byte of the containing aligned word and working toward the effective byte address. Use together with 'swl' to store a full word at an unaligned address.

Store Word Right : Store low-order 1 to 4 bytes of $t1 into memory, starting with high-order byte of word containing effective memory byte address and continuing through that byte address

Synchronize shared memory : Orders the loads and stores around it, so that another processor observes them in program order. This simulator runs a single processor and completes every access immediately, so there is nothing to reorder and 'sync' does nothing. It is accepted so that compiler output and real-world code assemble unchanged.

Synchronize shared memory (typed) : Like 'sync', but the operand selects which accesses to order. This simulator completes every access immediately, so the type is ignored and the instruction does nothing.

System call : Invokes an OS service identified by the integer in $v0. Common services: 1=print integer ($a0), 4=print string (addr in $a0), 5=read integer (result in $v0), 8=read string ($a0=buf addr, $a1=len), 10=exit. See the Help menu for the full list.

Trap if equal : Raises a trap exception if $t1 == $t2. In MARS this halts execution. On real hardware it triggers a trap handler. Useful as a guarded assertion or to catch forbidden conditions (e.g., division by zero guard).

Trap if equal to immediate : Raises a trap exception if $t1 == immediate (sign-extended to 32 bits). Immediate variant of 'teq'. Useful for checking a register against a known constant at runtime.

Trap if greater or equal (signed) : Raises a trap exception if $t1 >= $t2 (signed comparison).

Trap if greater or equal to immediate (signed) : Raises a trap if $t1 >= immediate (sign-extended to 32 bits).

Trap if greater or equal to immediate (unsigned) : Raises a trap if $t1 >= immediate using unsigned comparison. The immediate is sign-extended to 32 bits then interpreted as unsigned.

Trap if greater or equal (unsigned) : Raises a trap exception if $t1 >= $t2 using unsigned comparison. Treats both values as unsigned 32-bit integers.

Trap if less than (signed) : Raises a trap exception if $t1 < $t2 (signed comparison).

Trap if less than immediate (signed) : Raises a trap exception if $t1 < immediate (sign-extended to 32 bits).

Trap if less than immediate (unsigned) : Raises a trap exception if $t1 < immediate using unsigned comparison. The immediate is sign-extended to 32 bits then interpreted as unsigned.

Trap if less than (unsigned) : Raises a trap exception if $t1 < $t2 using unsigned comparison.

Trap if not equal : Raises a trap exception if $t1 != $t2. In MARS this halts execution. Opposite of 'teq'.

Trap if not equal to immediate : Raises a trap exception if $t1 != immediate (sign-extended to 32 bits).

Truncate double-precision to word : Converts the double-precision float in $f2 (even-numbered register) to a 32-bit integer by rounding toward zero (dropping the fractional part), storing the result in $f1.

Truncate single-precision to word : Converts the single-precision float in $f1 to a 32-bit integer by rounding toward zero (drops the fractional part), and stores the result in $f0. Equivalent to C-style (int) cast.

Unaligned Load Halfword : Set $t1 to the 16 bits, sign-extended, starting at effective memory byte address

Unaligned Load Halfword : Set $t1 to the 16 bits, zero-extended, starting at effective memory byte address

Unaligned Load Word : Set $t1 to the 32 bits starting at effective memory byte address

Unaligned Store Halfword: Store low-order halfword $t1 contents into the 16 bits starting at effective memory byte address

Unaligned Store Word : Store $t1 contents into the 32 bits starting at effective memory byte address

Wait for interrupt : Halts the processor until an interrupt arrives. This simulator delivers no interrupts, so there would be nothing to wake it; rather than hang, 'wait' does nothing and execution continues. It is accepted so that kernel-style code assembles unchanged.

Word swap bytes within halfwords : Sets $t1 to $t2 with the two bytes of each halfword exchanged, so 0xAABBCCDD becomes 0xBBAADDCC. Combined with 'rotr $t1,$t1,16' this reverses all four bytes, converting between little and big endian.

Bitwise XOR (exclusive OR) : Sets $t1 = $t2 ^ $t3. Each bit of $t1 is 1 if the corresponding bits in $t2 and $t3 differ. Used to toggle specific bits, detect differences, or implement simple encryption/checksums.

XOR : set $t1 to ($t2 bitwise-exclusive-OR 16-bit unsigned immediate)

XOR : set $t1 to ($t1 bitwise-exclusive-OR 16-bit unsigned immediate)

Bitwise XOR immediate : Sets $t1 = $t2 ^ immediate. The 16-bit immediate is zero-extended before the XOR. Useful for toggling specific bits.

XOR Immediate : set $t1 to ($t2 bitwise-exclusive-OR 32-bit immediate)

XOR Immediate : set $t1 to ($t1 bitwise-exclusive-OR 16-bit unsigned immediate)

XOR Immediate : set $t1 to ($t1 bitwise-exclusive-OR 32-bit immediate)