srl

Operands

$reg, $reg, imm

Variants

  • Shift right logical : Sets $t1 = $t2 >>> immediate (0-31 bits). Vacated bits on the left are filled with 0 (unsigned shift). Shifting right by n is equivalent to unsigned division by 2^n. Use 'sra' to preserve the sign bit instead. srl $t1,$t2,10

Shift right logical : Sets $t1 = $t2 >>> immediate (0-31 bits). Vacated bits on the left are filled with 0 (unsigned shift). Shifting right by n is equivalent to unsigned division by 2^n. Use 'sra' to preserve the sign bit instead.

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