Store conditional : Stores the value of $t1 into memory at address ($t2 + offset), then sets $t1 = 1 (success). In real multi-processor hardware this can fail (setting $t1 = 0) if another processor modified the target location since the preceding 'll'. Always succeeds in this simulator.
sc
Operands
$reg, [imm($reg) / ($reg) / imm / id / id($reg) / id+imm / id+imm($reg)]Variants
- Store conditional : Stores the value of $t1 into memory at address ($t2 + offset), then sets $t1 = 1 (success). In real multi-processor hardware this can fail (setting $t1 = 0) if another processor modified the target location since the preceding 'll'. Always succeeds in this simulator. sc $t1,-100($t2)
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,($t2)
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,-100
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,100
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,100000
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,100($t2)
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,100000($t2)
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,label
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,label($t2)
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,label+100000
- Store Conditional : Paired with Load Linked (ll) to perform atomic read-modify-write. Treated as equivalent to Store Word (sw) because MARS does not simulate multiple processors. sc $t1,label+100000($t2)
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