Shift right logical variable : Sets $t1 = $t2 >>> ($t3 & 31). Like 'srl' but the shift amount is taken from the lowest 5 bits of register $t3 rather than an immediate constant. Vacated bits are zero-filled.
srlv
Operands
$reg, $reg, $regVariants
- Shift right logical variable : Sets $t1 = $t2 >>> ($t3 & 31). Like 'srl' but the shift amount is taken from the lowest 5 bits of register $t3 rather than an immediate constant. Vacated bits are zero-filled. srlv $t1,$t2,$t3
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