Tests bit 0 of B.
bit
Operands
bit bit,r | bit bit,(rr) | bit bit,(ii+dd)Loading...
Variants
Every form of bit the assembler accepts. The cycles column counts clock
cycles, written as taken/not taken for the conditional forms.
| Instruction | Description | Flags | Bytes | Cycles |
|---|---|---|---|---|
| bit 0,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 0,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 0,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 0,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 0,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 0,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 0,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 0,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 1,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 1,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 1,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 1,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 1,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 1,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 1,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 1,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 2,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 2,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 2,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 2,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 2,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 2,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 2,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 2,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 3,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 3,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 3,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 3,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 3,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 3,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 3,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 3,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 4,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 4,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 4,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 4,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 4,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 4,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 4,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 4,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 5,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 5,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 5,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 5,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 5,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 5,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 5,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 5,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 6,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 6,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 6,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 6,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 6,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 6,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 6,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 6,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 7,b | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 7,c | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 7,d | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 7,e | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 7,h | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 7,l | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 7,(hl) | N=0P/V=*H=1ZS=* | 2 | 12 | |
| bit 7,a | N=0P/V=*H=1ZS=* | 2 | 8 | |
| bit 0,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 1,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 2,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 3,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 4,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 5,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 6,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 7,(ix+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 0,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 1,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 2,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 3,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 4,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 5,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 6,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 | |
| bit 7,(iy+dd) | N=0P/V=*H=1ZS=* | 4 | 20 |