JRCXZ - x86-64 instruction reference

jrcxzJump if rcx register is 0 
Jumps when rcx is zero, using an 8-bit displacement from the end of the instruction.
x86-64 and later
Intel's reference: Jcc 
CFPFAFZFSFDFOF –––––––
Changes no flag
Forms  jrcxz   
Operands imm8 A branch target, written as a label or address. NASM calculates the displacement from the end of the instruction. The displacement must fit a signed byte, -128 to 127. 
jrcxz tests rcx; jecxz tests ecx and uses the 32-bit address size in 64-bit mode. jcxz target tests cx and is unavailable in 64-bit mode because 16-bit addressing is unavailable. NASM also accepts jcxz target, ecx and jcxz target, rcx as explicit-counter aliases for jecxz and jrcxz.
The operand is a target label or address. NASM encodes a signed 8-bit displacement from the end of the instruction, reaching −128 through 127 bytes. There is no longer near encoding for these instructions.
 global _start

section .text
_start:
        mov rcx, 2
        jrcxz zero          ; jumps only when rcx is zero, without reading the flags
        mov rax, 1          ; runs, because rcx is 2
zero:

        mov rax, 60         ; syscall 60: exit
        xor rdi, rdi
        syscall