mov

Move

Copies the contents of the source (second) operand into the destination (first) operand.

8086 and later

Intel's reference: MOV

Used in

Getting started with x86-64x86-64 assembly
The 16 registers and their halvesx86-64 assembly
Memory, little endian and sizesx86-64 assembly
Bytes, words, dwords and qwordsx86-64 assembly
The x86-64 instruction setx86-64 assembly
Effective addressesx86-64 assembly
The flags registerx86-64 assembly
Sections, directives and labelsx86-64 assembly
Memory regions and executable filesx86-64 assembly
cmp and the conditional jumpsx86-64 assembly

CFPFAFZFSFDFOF –––––––

Changes no flag

Forms

mov , 8163264
mov , 8163264
mov , 8163264
mov , 8163264
mov ,
mov , 163264
mov ,
mov , 163264
mov , 8163264
mov , 8163264

Privileged

The processor reserves these for supervisor or kernel mode.

mov ,
mov ,
mov ,
mov ,

Operands

r/m: A general-purpose register or memory location matching the operation’s size, for example rax or qword [rbp-8]. The byte registers ah, bh, ch and dh cannot be used with a REX prefix, including when the memory address uses r8–r15.
reg: A general-purpose register matching the operation’s size, for example al, ax, eax or rax. The byte registers ah, bh, ch and dh cannot be used with a REX prefix, which is required by spl, bpl, sil, dil and r8–r15.
imm: An immediate value encoded in the instruction, written as a number, character or label. Its encoded width and any sign extension depend on the instruction; arithmetic immediates may be sign-extended, while shift counts are used without sign extension.
mem16: A 16-bit value in memory, for example word [rbx+8].
segreg: A segment register: es, cs, ss, ds, fs or gs.
acc: The accumulator matching the operation’s size: al, ax, eax or rax. A shorter encoding may be available.
moffs: An absolute memory address with no base or index register, such as [label], used by mov to transfer data to or from the accumulator.
reg64: A 64-bit general-purpose register: rax, rbx, rcx, rdx, rsi, rdi, rsp, rbp or r8 to r15.
creg: A control register defined by the processor, such as cr0, cr2, cr3, cr4 or cr8. Availability depends on the processor and execution mode.
dreg: A debug register, dr0 to dr7. dr4 and dr5 are legacy aliases whose availability depends on the processor’s debug configuration.

Register and memory data normally have the same width, and at most one operand can be memory.
Writing a 32-bit register clears the upper 32 bits of its 64-bit register: mov eax, -1 leaves rax = 0x00000000ffffffff. Writing ax or al preserves the remaining bits of rax.
A register-immediate move can load all 64 bits: mov rax, 0x123456789abcdef0 needs no special mnemonic. NASM chooses a shorter encoding when the same value can be obtained by a 32-bit register write or a sign-extended 32-bit immediate. For example, mov rax, 1 can use the former, while mov rax, -1 can use the latter. mov rax, strict qword 1 forces the full 64-bit immediate field.
A move of an immediate directly into 64-bit memory has only a 32-bit immediate field, sign-extended to 64 bits. Thus mov qword [rdi], -1 stores eight bytes of ones. To store an arbitrary 64-bit constant, first load it into a register, then store that register. A memory size such as qword specifies the stored width, not an immediate field of that width.
The accumulator memory-offset forms use al, ax, eax or rax and an absolute memory address; the address width and the data width are separate. CS cannot be a destination.

global _start

section .text
_start:
        mov rax, 12
        mov rbx, 5
        mov rcx, 3
        mov rsi, 9

        mov rax, rbx

        mov rax, 60         ; syscall 60: exit
        xor rdi, rdi
        syscall1
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