POP loads a value from the stack (from [SS:SP] or
[SS:ESP]) and then increments the stack pointer.
The address-size attribute of the instruction determines whether
SP or ESP is used as the stack pointer: to deliberately
override the default given by the BITS setting, you can use an
a16 or a32 prefix.
The operand-size attribute of the instruction determines whether the
stack pointer is incremented by 2 or 4: this means that segment
register pops in BITS 32 mode will pop 4 bytes off the stack and
discard the upper two of them. If you need to override that, you can
use an o16 or o32 prefix.
The above opcode listings give two forms for general-purpose
register pop instructions: for example, POP BX has the two forms
5B and 8F C3. NASM will always generate the shorter form
when given POP BX. NDISASM will disassemble both.
POP CS is not a documented instruction, and is not supported on
any processor above the 8086 (since they use 0Fh as an opcode
prefix for instruction set extensions). However, at least some 8086
processors do support it, and so NASM generates it for completeness.