RISC-V Complete Documentation

Instructions

add reg, reg, reg

Addition: set t1 to (t2 plus t3)

add t1,t2,t3

addi reg, reg, [imm / %lo(id)]

Addition immediate: set t1 to (t2 plus signed 12-bit immediate)

addi t1,t2,-100

Load Lower Address : Set t1 to t2 + lower 12-bit label's address

addi t1,t2,%lo(label)

addiw reg, reg, imm

Addition immediate: set t1 to (t2 plus signed 12-bit immediate) using only the lower 32 bits (64bit)

addiw t1,t2,-100

addw reg, reg, reg

Addition: set t1 to (t2 plus t3) using only the lower 32 bits (64bit)

addw t1,t2,t3

and reg, reg, reg

Bitwise AND : Set t1 to bitwise AND of t2 and t3

and t1,t2,t3

andi reg, reg, imm

Bitwise AND immediate : Set t1 to bitwise AND of t2 and sign-extended 12-bit immediate

andi t1,t2,-100

auipc reg, imm

Add upper immediate to pc: set t1 to (pc plus an upper 20-bit immediate)

auipc t1,100000

b id

Branch : Branch to statement at label unconditionally

b label

beq reg, reg, id

Branch if equal : Branch to statement at label's address if t1 and t2 are equal

beq t1,t2,label

beqz reg, id

Branch if EQual Zero : Branch to statement at label if t1 == 0

beqz t1,label

bge reg, reg, id

Branch if greater than or equal: Branch to statement at label's address if t1 is greater than or equal to t2

bge t1,t2,label

bgeu reg, reg, id

Branch if greater than or equal to (unsigned): Branch to statement at label's address if t1 is greater than or equal to t2 (with an unsigned interpretation)

bgeu t1,t2,label

bgez reg, id

Branch if Greater than or Equal to Zero : Branch to statement at label if t1 >= 0

bgez t1,label

bgt reg, reg, id

Branch if Greater Than : Branch to statement at label if t1 > t2

bgt t1,t2,label

bgtu reg, reg, id

Branch if Greater Than Unsigned: Branch to statement at label if t1 > t2 (unsigned compare)

bgtu t1,t2,label

bgtz reg, id

Branch if Greater Than Zero: Branch to statement at label if t1 > 0

bgtz t1,label

ble reg, reg, id

Branch if Less or Equal : Branch to statement at label if t1 <= t2

ble t1,t2,label

bleu reg, reg, id

Branch if Less or Equal Unsigned : Branch to statement at label if t1 <= t2 (unsigned compare)

bleu t1,t2,label

blez reg, id

Branch if Less than or Equal to Zero : Branch to statement at label if t1 <= 0

blez t1,label

blt reg, reg, id

Branch if less than: Branch to statement at label's address if t1 is less than t2

blt t1,t2,label

bltu reg, reg, id

Branch if less than (unsigned): Branch to statement at label's address if t1 is less than t2 (with an unsigned interpretation)

bltu t1,t2,label

bltz reg, id

Branch if Less Than Zero : Branch to statement at label if t1 < 0

bltz t1,label

bne reg, reg, id

Branch if not equal : Branch to statement at label's address if t1 and t2 are not equal

bne t1,t2,label

bnez reg, id

Branch if Not Equal Zero : Branch to statement at label if t1 != 0

bnez t1,label

call id

CALL: call a far-away subroutine

call label

csrc reg, csr

Clear bits in control and status register

csrc t1, fcsr

csrci csr, imm

Clear bits in control and status register

csrci fcsr, 100

csrr reg, csr

Read control and status register

csrr t1, fcsr

csrrc reg, csr, reg

Atomic Read/Clear CSR: read from the CSR into t0 and clear bits of the CSR according to t1

csrrc t0, fcsr, t1

csrrci reg, csr, imm

Atomic Read/Clear CSR Immediate: read from the CSR into t0 and clear bits of the CSR according to a constant

csrrci t0, fcsr, 10

csrrs reg, csr, reg

Atomic Read/Set CSR: read from the CSR into t0 and logical or t1 into the CSR

csrrs t0, fcsr, t1

csrrsi reg, csr, imm

Atomic Read/Set CSR Immediate: read from the CSR into t0 and logical or a constant into the CSR

csrrsi t0, fcsr, 10

csrrw reg, csr, reg

Atomic Read/Write CSR: read from the CSR into t0 and write t1 into the CSR

csrrw t0, fcsr, t1

csrrwi reg, csr, imm

Atomic Read/Write CSR Immediate: read from the CSR into t0 and write a constant into the CSR

csrrwi t0, fcsr, 10

csrs reg, csr

Set bits in control and status register

csrs t1, fcsr

csrsi csr, imm

Set bits in control and status register

csrsi fcsr, 100

csrw reg, csr

Write control and status register

csrw t1, fcsr

csrwi csr, imm

Write control and status register

csrwi fcsr, 100

div reg, reg, reg

Division: set t1 to the result of t2/t3

div t1,t2,t3

divu reg, reg, reg

Division: set t1 to the result of t2/t3 using unsigned division

divu t1,t2,t3

divuw reg, reg, reg

Division: set t1 to the result of t2/t3 using unsigned division limited to 32 bits (64bit)

divuw t1,t2,t3

divw reg, reg, reg

Division: set t1 to the result of t2/t3 using only the lower 32 bits (64bit)

divw t1,t2,t3

ebreak

Pause execution

ebreak

ecall

Issue a system call : Execute the system call specified by value in a7

ecall

fabs.d freg, freg

Set f1 to the absolute value of f2 (64 bit)

fabs.d f1, f2

fabs.s freg, freg

Set f1 to the absolute value of f2

fabs.s f1, f2

fadd.d freg, freg, freg, rounding

Floating ADD (64 bit): assigns f1 to f2 + f3

fadd.d f1, f2, f3, dyn fadd.d f1, f2, f3

fadd.s freg, freg, freg, rounding

Floating ADD: assigns f1 to f2 + f3

fadd.s f1, f2, f3, dyn fadd.s f1, f2, f3

fclass.d reg, freg

Classify a floating point number (64 bit)

fclass.d t1, f1

fclass.s reg, freg

Classify a floating point number

fclass.s t1, f1

fcvt.d.l freg, reg, rounding

Convert double from long: Assigns the value of t1 to f1 (64bit)

fcvt.d.l f1, t1, dyn

Convert double from signed 64 bit integer: Assigns the value of t1 to f1 (64bit)

fcvt.d.l f1, t1

fcvt.d.lu freg, reg, rounding

Convert double from unsigned long: Assigns the value of t1 to f1 (64bit)

fcvt.d.lu f1, t1, dyn

Convert double from unsigned 64 bit integer: Assigns the value of t1 to f1 (64bit)

fcvt.d.lu f1, t1

fcvt.d.s freg, freg, rounding

Convert a float to a double: Assigned the value of f2 to f1

fcvt.d.s f1, f2, dyn

Convert float to double: Assigned the value of f2 to f1

fcvt.d.s f1, f2

fcvt.d.w freg, reg, rounding

Convert double from integer: Assigns the value of t1 to f1

fcvt.d.w f1, t1, dyn

Convert double from signed integer: Assigns the value of t1 to f1

fcvt.d.w f1, t1

fcvt.d.wu freg, reg, rounding

Convert double from unsigned integer: Assigns the value of t1 to f1

fcvt.d.wu f1, t1, dyn fcvt.d.wu f1, t1

fcvt.l.d reg, freg, rounding

Convert 64 bit integer from double: Assigns the value of f1 (rounded) to t1 (64bit)

fcvt.l.d t1, f1, dyn

Convert signed 64 bit integer from double: Assigns the value of f1 (rounded) to t1 (64bit)

fcvt.l.d t1, f1

fcvt.l.s reg, freg, rounding

Convert 64 bit integer from float: Assigns the value of f1 (rounded) to t1 (64bit)

fcvt.l.s t1, f1, dyn

Convert signed 64 bit integer from float: Assigns the value of f1 (rounded) to t1 (64bit)

fcvt.l.s t1, f1

fcvt.lu.d reg, freg, rounding

Convert unsigned 64 bit integer from double: Assigns the value of f1 (rounded) to t1 (64bit)

fcvt.lu.d t1, f1, dyn fcvt.lu.d t1, f1

fcvt.lu.s reg, freg, rounding

Convert unsigned 64 bit integer from float: Assigns the value of f1 (rounded) to t1 (64bit)

fcvt.lu.s t1, f1, dyn fcvt.lu.s t1, f1

fcvt.s.d freg, freg, rounding

Convert a double to a float: Assigned the value of f2 to f1

fcvt.s.d f1, f2, dyn

Convert double to float: Assigned the value of f2 to f1

fcvt.s.d f1, f2

fcvt.s.l freg, reg, rounding

Convert float from long: Assigns the value of t1 to f1 (64bit)

fcvt.s.l f1, t1, dyn

Convert float from signed 64 bit integer: Assigns the value of t1 to f1 (64bit)

fcvt.s.l f1, t1

fcvt.s.lu freg, reg, rounding

Convert float from unsigned long: Assigns the value of t1 to f1 (64bit)

fcvt.s.lu f1, t1, dyn

Convert float from unsigned 64 bit integer: Assigns the value of t1 to f1 (64bit)

fcvt.s.lu f1, t1

fcvt.s.w freg, reg, rounding

Convert float from integer: Assigns the value of t1 to f1

fcvt.s.w f1, t1, dyn

Convert float from signed integer: Assigns the value of t1 to f1

fcvt.s.w f1, t1

fcvt.s.wu freg, reg, rounding

Convert float from unsigned integer: Assigns the value of t1 to f1

fcvt.s.wu f1, t1, dyn fcvt.s.wu f1, t1

fcvt.w.d reg, freg, rounding

Convert integer from double: Assigns the value of f1 (rounded) to t1

fcvt.w.d t1, f1, dyn

Convert signed integer from double: Assigns the value of f1 (rounded) to t1

fcvt.w.d t1, f1

fcvt.w.s reg, freg, rounding

Convert integer from float: Assigns the value of f1 (rounded) to t1

fcvt.w.s t1, f1, dyn

Convert signed integer from float: Assigns the value of f1 (rounded) to t1

fcvt.w.s t1, f1

fcvt.wu.d reg, freg, rounding

Convert unsinged integer from double: Assigns the value of f1 (rounded) to t1

fcvt.wu.d t1, f1, dyn

Convert unsigned integer from double: Assigns the value of f1 (rounded) to t1

fcvt.wu.d t1, f1

fcvt.wu.s reg, freg, rounding

Convert unsinged integer from float: Assigns the value of f1 (rounded) to t1

fcvt.wu.s t1, f1, dyn

Convert unsigned integer from float: Assigns the value of f1 (rounded) to t1

fcvt.wu.s t1, f1

fdiv.d freg, freg, freg, rounding

Floating DIVide (64 bit): assigns f1 to f2 / f3

fdiv.d f1, f2, f3, dyn fdiv.d f1, f2, f3

fdiv.s freg, freg, freg, rounding

Floating DIVide: assigns f1 to f2 / f3

fdiv.s f1, f2, f3, dyn fdiv.s f1, f2, f3

fence imm, imm

Ensure that IO and memory accesses before the fence happen before the following IO and memory accesses as viewed by a different thread

fence 1, 1

fence.i

Ensure that stores to instruction memory are visible to instruction fetches

fence.i

feq.d reg, freg, freg

Floating EQuals (64 bit): if f1 = f2, set t1 to 1, else set t1 to 0

feq.d t1, f1, f2

feq.s reg, freg, freg

Floating EQuals: if f1 = f2, set t1 to 1, else set t1 to 0

feq.s t1, f1, f2

fge.d reg, freg, freg

Floating Greater Than or Equal (64 bit): if f2 >= f3, set t1 to 1, else set t1 to 0

fge.d t1, f2, f3

fge.s reg, freg, freg

Floating Greater Than or Equal: if f2 >= f3, set t1 to 1, else set t1 to 0

fge.s t1, f2, f3

fgt.d reg, freg, freg

Floating Greater Than (64 bit): if f2 > f3, set t1 to 1, else set t1 to 0

fgt.d t1, f2, f3

fgt.s reg, freg, freg

Floating Greater Than: if f2 > f3, set t1 to 1, else set t1 to 0

fgt.s t1, f2, f3

fld freg, [imm(reg) / (reg) / imm / id / %lo(id)], [reg / (reg)]

Load a double from memory

fld f1, -100(t1)

Load Word: Set f1 to 64-bit value from effective memory word address

fld f1,(t2) fld f1,-100

Load Word: Set f1 to 64-bit value from effective memory word address using t3 as a temporary

fld f1,10000000,t3 fld f1,label, t3

Load from Address

fld f1,%lo(label)(t2)

fle.d reg, freg, freg

Floating Less than or Equals (64 bit): if f1 <= f2, set t1 to 1, else set t1 to 0

fle.d t1, f1, f2

fle.s reg, freg, freg

Floating Less than or Equals: if f1 <= f2, set t1 to 1, else set t1 to 0

fle.s t1, f1, f2

flt.d reg, freg, freg

Floating Less Than (64 bit): if f1 < f2, set t1 to 1, else set t1 to 0

flt.d t1, f1, f2

flt.s reg, freg, freg

Floating Less Than: if f1 < f2, set t1 to 1, else set t1 to 0

flt.s t1, f1, f2

flw freg, [imm(reg) / (reg) / imm / id / %lo(id)], [reg / (reg)]

Load a float from memory

flw f1, -100(t1)

Load Word Coprocessor 1 : Set f1 to 32-bit value from effective memory word address

flw f1,(t2) flw f1,-100

Load Word Coprocessor 1 : Set f1 to 32-bit value from effective memory word address using t3 as a temporary

flw f1,10000000,t3 flw f1,label, t3

Load from Address

flw f1,%lo(label)(t2)

fmadd.d freg, freg, freg, freg, rounding

Fused Multiply Add (64 bit): Assigns f2*f3+f4 to f1

fmadd.d f1, f2, f3, f4, dyn fmadd.d f1, f2, f3, f4

fmadd.s freg, freg, freg, freg, rounding

Fused Multiply Add: Assigns f2*f3+f4 to f1

fmadd.s f1, f2, f3, f4, dyn fmadd.s f1, f2, f3, f4

fmax.d freg, freg, freg

Floating MAXimum (64 bit): assigns f1 to the larger of f1 and f3

fmax.d f1, f2, f3

fmax.s freg, freg, freg

Floating MAXimum: assigns f1 to the larger of f1 and f3

fmax.s f1, f2, f3

fmin.d freg, freg, freg

Floating MINimum (64 bit): assigns f1 to the smaller of f1 and f3

fmin.d f1, f2, f3

fmin.s freg, freg, freg

Floating MINimum: assigns f1 to the smaller of f1 and f3

fmin.s f1, f2, f3

fmsub.d freg, freg, freg, freg, rounding

Fused Multiply Subatract: Assigns f2*f3-f4 to f1

fmsub.d f1, f2, f3, f4, dyn

Fused Multiply Subatract (64 bit): Assigns f2*f3-f4 to f1

fmsub.d f1, f2, f3, f4

fmsub.s freg, freg, freg, freg, rounding

Fused Multiply Subatract: Assigns f2*f3-f4 to f1

fmsub.s f1, f2, f3, f4, dyn fmsub.s f1, f2, f3, f4

fmul.d freg, freg, freg, rounding

Floating MULtiply (64 bit): assigns f1 to f2 * f3

fmul.d f1, f2, f3, dyn fmul.d f1, f2, f3

fmul.s freg, freg, freg, rounding

Floating MULtiply: assigns f1 to f2 * f3

fmul.s f1, f2, f3, dyn fmul.s f1, f2, f3

fmv.d freg, freg

Move the value of f2 to f1 (64 bit)

fmv.d f1, f2

fmv.d.x freg, reg

Move float: move bits representing a double from an 64 bit integer register (64bit)

fmv.d.x f1, t1

fmv.s freg, freg

Move the value of f2 to f1

fmv.s f1, f2

fmv.s.x freg, reg

Move float: move bits representing a float from an integer register

fmv.s.x f1, t1

fmv.w.x freg, reg

Move float (New mnemonic): move bits representing a float from an integer register

fmv.w.x f1, t1

fmv.x.d reg, freg

Move double: move bits representing a double to an 64 bit integer register (64bit)

fmv.x.d t1, f1

fmv.x.s reg, freg

Move float: move bits representing a float to an integer register

fmv.x.s t1, f1

fmv.x.w reg, freg

Move float (New mnemonic): move bits representing a float to an integer register

fmv.x.w t1, f1

fneg.d freg, freg

Set f1 to the negation of f2 (64 bit)

fneg.d f1, f2

fneg.s freg, freg

Set f1 to the negation of f2

fneg.s f1, f2

fnmadd.d freg, freg, freg, freg, rounding

Fused Negate Multiply Add (64 bit): Assigns -(f2*f3+f4) to f1

fnmadd.d f1, f2, f3, f4, dyn fnmadd.d f1, f2, f3, f4

fnmadd.s freg, freg, freg, freg, rounding

Fused Negate Multiply Add: Assigns -(f2*f3+f4) to f1

fnmadd.s f1, f2, f3, f4, dyn fnmadd.s f1, f2, f3, f4

fnmsub.d freg, freg, freg, freg, rounding

Fused Negated Multiply Subatract: Assigns -(f2*f3-f4) to f1

fnmsub.d f1, f2, f3, f4, dyn

Fused Negated Multiply Subatract (64 bit): Assigns -(f2*f3-f4) to f1

fnmsub.d f1, f2, f3, f4

fnmsub.s freg, freg, freg, freg, rounding

Fused Negated Multiply Subatract: Assigns -(f2*f3-f4) to f1

fnmsub.s f1, f2, f3, f4, dyn fnmsub.s f1, f2, f3, f4

frcsr reg

Read FP control/status register

frcsr t1

frflags reg

Read FP exception flags

frflags t1

frrm reg

Read FP rounding mode

frrm t1

frsr reg

Alias for frcsr t1

frsr t1

fscsr reg, reg

Swap FP control/status register

fscsr t1, t2

Write FP control/status register

fscsr t1

fsd freg, [imm(reg) / (reg) / imm / id], reg

Store a double to memory

fsd f1, -100(t1)

Store Word: Store 64-bit value from f1 to effective memory word address

fsd f1,(t2) fsd f1,-100

Store Word: Store 64-bit value from f1 to effective memory word address using t3 as a temporary

fsd f1,10000000,t3 fsd f1,label, t3

fsflags reg, reg

Swap FP exception flags

fsflags t1, t2

Write FP exception flags

fsflags t1

fsgnj.d freg, freg, freg

Floating point sign injection (64 bit): replace the sign bit of f2 with the sign bit of f3 and assign it to f1

fsgnj.d f1, f2, f3

fsgnj.s freg, freg, freg

Floating point sign injection: replace the sign bit of f2 with the sign bit of f3 and assign it to f1

fsgnj.s f1, f2, f3

fsgnjn.d freg, freg, freg

Floating point sign injection (inverted 64 bit): replace the sign bit of f2 with the opposite of sign bit of f3 and assign it to f1

fsgnjn.d f1, f2, f3

fsgnjn.s freg, freg, freg

Floating point sign injection (inverted): replace the sign bit of f2 with the opposite of sign bit of f3 and assign it to f1

fsgnjn.s f1, f2, f3

fsgnjx.d freg, freg, freg

Floating point sign injection (xor 64 bit): xor the sign bit of f2 with the sign bit of f3 and assign it to f1

fsgnjx.d f1, f2, f3

fsgnjx.s freg, freg, freg

Floating point sign injection (xor): xor the sign bit of f2 with the sign bit of f3 and assign it to f1

fsgnjx.s f1, f2, f3

fsqrt.d freg, freg, rounding

Floating SQuare RooT (64 bit): Assigns f1 to the square root of f2

fsqrt.d f1, f2, dyn fsqrt.d f1, f2

fsqrt.s freg, freg, rounding

Floating SQuare RooT: Assigns f1 to the square root of f2

fsqrt.s f1, f2, dyn fsqrt.s f1, f2

fsrm reg, reg

Swap FP rounding mode

fsrm t1, t2

Write FP rounding mode

fsrm t1

fssr reg, reg

Alias for fscsr t1, t2

fssr t1, t2

Alias for fscsr t1

fssr t1

fsub.d freg, freg, freg, rounding

Floating SUBtract (64 bit): assigns f1 to f2 - f3

fsub.d f1, f2, f3, dyn fsub.d f1, f2, f3

fsub.s freg, freg, freg, rounding

Floating SUBtract: assigns f1 to f2 - f3

fsub.s f1, f2, f3, dyn fsub.s f1, f2, f3

fsw freg, [imm(reg) / (reg) / imm / id], reg

Store a float to memory

fsw f1, -100(t1)

Store Word Coprocessor 1 : Store 32-bit value from f1 to effective memory word address

fsw f1,(t2) fsw f1,-100

Store Word Coprocessor 1 : Store 32-bit value from f1 to effective memory word address using t3 as a temporary

fsw f1,10000000,t3 fsw f1,label, t3

j id

Jump : Jump to statement at label

j label

jal [reg / id], id

Jump and link : Set t1 to Program Counter (return address) then jump to statement at target address

jal t1, target

Jump And Link: Jump to statement at label and set the return address to ra

jal label

jalr reg, [reg / imm / imm(reg)], imm

Jump and link register: Set t1 to Program Counter (return address) then jump to statement at t2 + immediate

jalr t1, t2, -100

Jump And Link Register: Jump to address in t0 and set the return address to ra

jalr t0 jalr t0, -100

Jump And Link Register: Jump to address in t1 and set the return address to t0

jalr t0,-100(t1)

jr reg, imm

Jump Register: Jump to address in t0

jr t0 jr t0, -100

la reg, id

Load Address : Set t1 to label's address

la t1,label

lb reg, [imm(reg) / (reg) / imm / id / %lo(id)], (reg)

Set t1 to sign-extended 8-bit value from effective memory byte address

lb t1, -100(t2)

Load Byte : Set t1 to sign-extended 8-bit value from effective memory byte address

lb t1,(t2)

Load Byte : Set $1 to sign-extended 8-bit value from effective memory byte address

lb t1,-100

Load Byte : Set $t1 to sign-extended 8-bit value from effective memory byte address

lb t1,10000000 lb t1,label

Load from Address

lb t1,%lo(label)(t2)

lbu reg, [imm(reg) / (reg) / imm / id]

Set t1 to zero-extended 8-bit value from effective memory byte address

lbu t1, -100(t2)

Load Byte Unsigned : Set $t1 to zero-extended 8-bit value from effective memory byte address

lbu t1,(t2) lbu t1,-100

Load Byte Unsigned : Set t1 to zero-extended 8-bit value from effective memory byte address

lbu t1,10000000 lbu t1,label

ld reg, [imm(reg) / (reg) / imm / id / %lo(id)], (reg)

Set t1 to contents of effective memory double word address (64bit)

ld t1, -100(t2)

Load Double word : Set t1 to contents of effective memory word address (64bit)

ld t1,(t2) ld t1,-100 ld t1,10000000

Load Double word : Set t1 to contents of memory word at label's address (64bit)

ld t1,label

Load from Address (64bit)

ld t1,%lo(label)(t2)

lh reg, [imm(reg) / (reg) / imm / id / %lo(id)], (reg)

Set t1 to sign-extended 16-bit value from effective memory halfword address

lh t1, -100(t2)

Load Halfword : Set t1 to sign-extended 16-bit value from effective memory halfword address

lh t1,(t2) lh t1,-100 lh t1,10000000 lh t1,label

Load from Address

lh t1,%lo(label)(t2)

lhu reg, [imm(reg) / (reg) / imm / id]

Set t1 to zero-extended 16-bit value from effective memory halfword address

lhu t1, -100(t2)

Load Halfword Unsigned : Set t1 to zero-extended 16-bit value from effective memory halfword address

lhu t1,(t2) lhu t1,-100 lhu t1,10000000 lhu t1,label

li reg, imm

Load Immediate : Set t1 to 12-bit immediate (sign-extended)

li t1,-100

Load Immediate : Set t1 to 32-bit immediate

li t1,10000000

Load Immediate : Set t1 to 12-bit immediate (sign-extended) (64bit)

li t1,-100

Load Immediate : Set t1 to 32-bit immediate (sign-extended) (64bit)

li t1,10000000

Load Immediate : Set t1 to 64-bit immediate (64bit)

li t1,1000000000000000

lui reg, [imm / %hi(id)]

Load upper immediate: set t1 to 20-bit followed by 12 0s

lui t1,100000

Load Upper Address : Set t1 to upper 20-bit label's address

lui t1,%hi(label)

lw reg, [imm(reg) / (reg) / imm / id / %lo(id)], (reg)

Set t1 to contents of effective memory word address

lw t1, -100(t2)

Load Word : Set t1 to contents of effective memory word address

lw t1,(t2) lw t1,-100 lw t1,10000000

Load Word : Set t1 to contents of memory word at label's address

lw t1,label

Load from Address

lw t1,%lo(label)(t2)

lwu reg, imm(reg)

Set t1 to contents of effective memory word address without sign-extension (64bit)

lwu t1, -100(t2)

mul reg, reg, reg

Multiplication: set t1 to the lower 32 bits of t2*t3

mul t1,t2,t3

mulh reg, reg, reg

Multiplication: set t1 to the upper 32 bits of t2*t3 using signed multiplication

mulh t1,t2,t3

mulhsu reg, reg, reg

Multiplication: set t1 to the upper 32 bits of t2*t3 where t2 is signed and t3 is unsigned

mulhsu t1,t2,t3

mulhu reg, reg, reg

Multiplication: set t1 to the upper 32 bits of t2*t3 using unsigned multiplication

mulhu t1,t2,t3

mulw reg, reg, reg

Multiplication: set t1 to the lower 32 bits of t2*t3 using only the lower 32 bits of the input (64bit)

mulw t1,t2,t3

mv reg, reg

MoVe : Set t1 to contents of t2

mv t1,t2

neg reg, reg

NEGate : Set t1 to negation of t2

neg t1,t2

negw reg, reg

NEGate Word: Set t1 to negation of t2 (only lower 32 bits) (64bit)

negw t1, t2

nop

NO OPeration

nop

not reg, reg

Bitwise NOT (bit inversion)

not t1,t2

or reg, reg, reg

Bitwise OR : Set t1 to bitwise OR of t2 and t3

or t1,t2,t3

ori reg, reg, imm

Bitwise OR immediate : Set t1 to bitwise OR of t2 and sign-extended 12-bit immediate

ori t1,t2,-100

rdcycle reg

Read from cycle

rdcycle t1

rdcycleh reg

Read from cycleh

rdcycleh t1

rdinstret reg

Read from instret

rdinstret t1

rdinstreth reg

Read from instreth

rdinstreth t1

rdtime reg

Read from time

rdtime t1

rdtimeh reg

Read from timeh

rdtimeh t1

rem reg, reg, reg

Remainder: set t1 to the remainder of t2/t3

rem t1,t2,t3

remu reg, reg, reg

Remainder: set t1 to the remainder of t2/t3 using unsigned division

remu t1,t2,t3

remuw reg, reg, reg

Remainder: set t1 to the remainder of t2/t3 using unsigned division limited to 32 bits (64bit)

remuw t1,t2,t3

remw reg, reg, reg

Remainder: set t1 to the remainder of t2/t3 using only the lower 32 bits (64bit)

remw t1,t2,t3

ret

Return: return from a subroutine

ret

sb reg, [imm(reg) / (reg) / imm / id], reg

Store byte : Store the low-order 8 bits of t1 into the effective memory byte address

sb t1, -100(t2)

Store Byte : Store the low-order 8 bits of t1 into the effective memory byte address

sb t1,(t2)

Store Byte : Store the low-order 8 bits of $t1 into the effective memory byte address

sb t1,-100 sb t1,10000000,t2 sb t1,label,t2

sd reg, imm(reg)

Store double word : Store contents of t1 into effective memory double word address (64bit)

sd t1, -100(t2)

seqz reg, reg

Set EQual to Zero : if t2 == 0 then set t1 to 1 else 0

seqz t1,t2

sext.b reg, reg

Sign EXTend Byte: extract the low byte from t2 and sign extend it into t1

sext.b t1, t2

Sign EXTend Byte: extract the low byte from t2 and sign extend it into t1 (64bit)

sext.b t1, t2

sext.h reg, reg

Sign EXTend Half: extract the low 16 bit from t2 and sign extend it into t1

sext.h t1, t2

Sign EXTend Half: extract the low 16 bit from t2 and sign extend it into t1 (64bit)

sext.h t1, t2

sext.w reg, reg

Sign EXTend Word: extract the low 32-bits from t2 and sign extend it into t1 (64bit)

sext.w t1, t2

sgt reg, reg, reg

Set Greater Than : if t2 greater than t3 then set t1 to 1 else 0

sgt t1,t2,t3

sgtu reg, reg, reg

Set Greater Than Unsigned : if t2 greater than t3 (unsigned compare) then set t1 to 1 else 0

sgtu t1,t2,t3

sgtz reg, reg

Set Greater Than Zero : if t2 > 0 then set t1 to 1 else 0

sgtz t1,t2

sh reg, [imm(reg) / (reg) / imm / id], reg

Store halfword : Store the low-order 16 bits of t1 into the effective memory halfword address

sh t1, -100(t2)

Store Halfword : Store the low-order 16 bits of $1 into the effective memory halfword address

sh t1,(t2)

Store Halfword : Store the low-order 16 bits of $t1 into the effective memory halfword address

sh t1,-100

Store Halfword : Store the low-order 16 bits of t1 into the effective memory halfword address using t2 as a temporary

sh t1,10000000,t2 sh t1,label,t2

sll reg, reg, reg

Shift left logical: Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3

sll t1,t2,t3

slli reg, reg, imm

Shift left logical : Set t1 to result of shifting t2 left by number of bits specified by immediate

slli t1,t2,10

Shift left logical : Set t1 to result of shifting t2 left by number of bits specified by immediate (64bit)

slli t1,t2,33

slliw reg, reg, imm

Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by immediate (64bit)

slliw t1,t2,10

sllw reg, reg, reg

Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3 (64bit)

sllw t1,t2,t3

slt reg, reg, reg

Set less than : If t2 is less than t3, then set t1 to 1 else set t1 to 0

slt t1,t2,t3

slti reg, reg, imm

Set less than immediate : If t2 is less than sign-extended 12-bit immediate, then set t1 to 1 else set t1 to 0

slti t1,t2,-100

sltiu reg, reg, imm

Set less than immediate unsigned : If t2 is less than sign-extended 16-bit immediate using unsigned comparison, then set t1 to 1 else set t1 to 0

sltiu t1,t2,-100

sltu reg, reg, reg

Set less than : If t2 is less than t3 using unsigned comparision, then set t1 to 1 else set t1 to 0

sltu t1,t2,t3

sltz reg, reg

Set Less Than Zero : if t2 < 0 then set t1 to 1 else 0

sltz t1,t2

snez reg, reg

Set Not Equal to Zero : if t2 != 0 then set t1 to 1 else 0

snez t1,t2

sra reg, reg, reg

Shift right arithmetic: Set t1 to result of sign-extended shifting t2 right by number of bits specified by value in low-order 5 bits of t3

sra t1,t2,t3

srai reg, reg, imm

Shift right arithmetic : Set t1 to result of sign-extended shifting t2 right by number of bits specified by immediate

srai t1,t2,10

Shift right arithmetic : Set t1 to result of sign-extended shifting t2 right by number of bits specified by immediate (64bit)

srai t1,t2,33

sraiw reg, reg, imm

Shift right arithmetic (32 bit): Set t1 to result of sign-extended shifting t2 right by number of bits specified by immediate (64bit)

sraiw t1,t2,10

sraw reg, reg, reg

Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3 (64bit)

sraw t1,t2,t3

srl reg, reg, reg

Shift right logical: Set t1 to result of shifting t2 right by number of bits specified by value in low-order 5 bits of t3

srl t1,t2,t3

srli reg, reg, imm

Shift right logical : Set t1 to result of shifting t2 right by number of bits specified by immediate

srli t1,t2,10

Shift right logical : Set t1 to result of shifting t2 right by number of bits specified by immediate (64bit)

srli t1,t2,33

srliw reg, reg, imm

Shift right logical (32 bit): Set t1 to result of shifting t2 right by number of bits specified by immediate (64bit)

srliw t1,t2,10

srlw reg, reg, reg

Shift left logical (32 bit): Set t1 to result of shifting t2 left by number of bits specified by value in low-order 5 bits of t3 (64bit)

srlw t1,t2,t3

sub reg, reg, reg

Subtraction: set t1 to (t2 minus t3)

sub t1,t2,t3

subw reg, reg, reg

Subtraction: set t1 to (t2 minus t3) using only the lower 32 bits (64bit)

subw t1,t2,t3

sw reg, [imm(reg) / (reg) / imm / id], reg

Store word : Store contents of t1 into effective memory word address

sw t1, -100(t2)

Store Word : Store t1 contents into effective memory word address

sw t1,(t2)

Store Word : Store $t1 contents into effective memory word address

sw t1,-100

Store Word : Store $t1 contents into effective memory word address using t2 as a temporary

sw t1,10000000,t2

Store Word : Store $t1 contents into memory word at label's address using t2 as a temporary

sw t1,label,t2

tail id

TAIL call: tail call (call without saving return address)a far-away subroutine

tail label

uret

Return from handling an interrupt or exception (to uepc)

uret

wfi

Wait for Interrupt

wfi

xor reg, reg, reg

Bitwise XOR : Set t1 to bitwise XOR of t2 and t3

xor t1,t2,t3

xori reg, reg, imm

Bitwise XOR immediate : Set t1 to bitwise XOR of t2 and sign-extended 12-bit immediate

xori t1,t2,-100

zext.b reg, reg

Zero EXTend Byte: extract the low byte into t1

zext.b t1, t2

Zero EXTend Byte: extract the low byte into t1 (64bit)

zext.b t1, t2

zext.h reg, reg

Zero EXTend Half: extract the low 16 bit into t1

zext.h t1, t2

Zero EXTend Half: extract the low 16 bit into t1 (64bit)

zext.h t1, t2

zext.w reg, reg

Zero EXTend Word: extract the low 32-bits from t2 into t1 (64bit)

zext.w t1, t2

Directives

RISC-V directives are used to define the structure of the program. They are not instructions that are executed by the CPU, but rather instructions that are used by the assembler to define the structure of the program.

.data

Subsequent items stored in Data segment at next available address

.text

Subsequent items (instructions) stored in Text segment at next available address

.word

Store the listed value(s) as 32 bit words on word boundary

.dword

Store the listed value(s) as 64 bit double-word on word boundary

.ascii

Store the string in the Data segment but do not add null terminator

.asciz

Store the string in the Data segment and add null terminator

.string

Alias for .asciz

.byte

Store the listed value(s) as 8 bit bytes

.align

Align next data item on specified byte boundary (0=byte, 1=half, 2=word, 3=double)

.half

Store the listed value(s) as 16 bit halfwords on halfword boundary

.space

Reserve the next specified number of bytes in Data segment

.double

Store the listed value(s) as double precision floating point

.float

Store the listed value(s) as single precision floating point

.extern

Declare the listed label and byte length to be a global data field

.globl

Declare the listed label(s) as global to enable referencing from other files

.global

Declare the listed label(s) as global to enable referencing from other files

.eqv

Substitute second operand for first. First operand is symbol, second operand is expression (like #define)

.macro

Begin macro definition. See .end_macro

.end_macro

End macro definition. See .macro

.include

Insert the contents of the specified file. Put filename in quotes.

.section

Allows specifying sections without .text or .data directives. Included for gcc comparability

Syscalls

RISC-V syscalls are used to make requests to the operating system. They are not instructions that are executed by the CPU, but rather instructions that are used by the simulator to make requests to the operating system.

Each syscall has a unique code that is used to identify it. You must put the syscall code inside the the a7 register before calling the ecall instruction.

As an example:

# Load the integer 42 into register a0, which is
# the register that will be printed by the syscall
li a0, 42

# Set the syscall code for printing an integer
li a7, 1
ecall

1 - Print integer

Arguments

a0
integer to print

2 - Print float

Arguments

f12
float to print

3 - Print double

Arguments

f12
double to print

4 - Print string

Arguments

a0
address of null-terminated string to print

5 - Read integer

Result

v0
contains integer read

6 - Read float

Result

f0
contains float read

7 - Read double

Result

f0
contains double read

8 - Read string

Service 8 - Follows semantics of UNIX 'fgets'. For specified length n, string can be no longer than n-1. If less than that, adds newline to end. In either case, then pads with null byte If n = 1, input is ignored and null byte placed at buffer address. If n < 1, input is ignored and nothing is written to the buffer.

Arguments

a0
address of input buffer
a1
maximum number of characters to read

9 - Sbrk (allocate heap memory)

Result

v0
contains address of allocated memory

Arguments

a0
number of bytes to allocate

10 - Exit (terminate execution)

11 - Print character

Service 11 - Prints ASCII character corresponding to contents of low-order byte.

Arguments

a0
character to print

12 - Read character

Result

v0
contains character read

17 - Get cwd

30 - Time (system time)

Service 30 - System time as milliseconds since 1 January 1970.

Result

a0
low order 32 bits of system time
a1
high order 32 bits of system time

34 - Print integer in hexadecimal

Displayed value is 8 hexadecimal digits, left-padding with zeroes if necessary.

Arguments

a0
integer to print

35 - Print integer in binary

Displayed value is 32 bits, left-padding with zeroes if necessary.

Arguments

a0
integer to print

36 - Print integer as unsigned

Displayed as unsigned decimal value.

Arguments

a0
integer to print

41 - Random int

Each stream (identified by a0 contents) is modeled by a different Random object. There are no default seed values, so use the Set Seed service (40) if replicated random sequences are desired.

Result

a0
contains the next pseudorandom, uniformly distributed int value from this random number generator's sequence

Arguments

a0
i.d. of pseudorandom number generator (any int)

42 - Random int range

Each stream (identified by a0 contents) is modeled by a different Random object. There are no default seed values, so use the Set Seed service (40) if replicated random sequences are desired.

Result

a0
contains pseudorandom, uniformly distributed int value in the range 0 <= [int] < [upper bound], drawn from this random number generator's sequence

Arguments

a0
i.d. of pseudorandom number generator (any int)
a1
upper bound of range of returned values

43 - Random float

Each stream (identified by a0 contents) is modeled by a different Random object. There are no default seed values, so use the Set Seed service (40) if replicated random sequences are desired.

Result

f0
contains the next pseudorandom, uniformly distributed float value in the range 0.0 <= f < 1.0 from this random number generator's sequence

Arguments

a0
i.d. of pseudorandom number generator (any int)

44 - Random double

Each stream (identified by a0 contents) is modeled by a different Random object. There are no default seed values, so use the Set Seed service (40) if replicated random sequences are desired.

Result

f0
contains the next pseudorandom, uniformly distributed double value in the range 0.0 <= f < 1.0 from this random number generator's sequence

Arguments

a0
i.d. of pseudorandom number generator (any int)

50 - ConfirmDialog

Result

a0
contains value of user-chosen option 0: Yes 1: No 2: Cancel

Arguments

a0
address of null-terminated string that is the message to user

51 - InputDialogInt

Result

a0
contains int read
a1
contains status value 0: OK status -1: input data cannot be correctly parsed -2: Cancel was chosen -3: OK was chosen but no data had been input into field

Arguments

a0
address of null-terminated string that is the message to user

52 - InputDialogFloat

Result

f0
contains float read
a1
contains status value 0: OK status -1: input data cannot be correctly parsed -2: Cancel was chosen -3: OK was chosen but no data had been input into field

Arguments

a0
address of null-terminated string that is the message to user

53 - InputDialogDouble

Result

f0
contains double read
a1
contains status value 0: OK status -1: input data cannot be correctly parsed -2: Cancel was chosen -3: OK was chosen but no data had been input into field

Arguments

a0
address of null-terminated string that is the message to user

54 - InputDialogString

See Service 8 note below table

Result

a1
contains status value 0: OK status. Buffer contains the input string. -2: Cancel was chosen. No change to buffer. -3: OK was chosen but no data had been input into field. No change to buffer. -4: length of the input string exceeded the specified maximum. Buffer contains the maximum allowable input string plus a terminating null.

Arguments

a0
address of null-terminated string that is the message to user
a1
address of input buffer
a2
maximum number of characters to read

55 - MessageDialog

Arguments

a0
address of null-terminated string that is the message to user
a1
the type of message to be displayed: 0: error message, indicated by Error icon 1: information message, indicated by Information icon 2: warning message, indicated by Warning icon 3: question message, indicated by Question icon other: plain message (no icon displayed)

56 - MessageDialogInt

Arguments

a0
address of null-terminated string that is an information-type message to user
a1
int value to display in string form after the first string

57 - Close file

Arguments

a0
file descriptor

58 - MessageDialogDouble

Arguments

a0
address of null-terminated string that is an information-type message to user
f12
double value to display in string form after the first string

59 - MessageDialogString

Arguments

a0
address of null-terminated string that is an information-type message to user
a1
address of null-terminated string to display after the first string

60 - MessageDialogFloat

Arguments

a0
address of null-terminated string that is an information-type message to user
f12
float value to display in string form after the first string

63 - Read from file

Result

v0
contains number of characters read (0 if end-of-file, negative if error)

Arguments

a0
file descriptor
a1
address of input buffer
a2
maximum number of characters to read

64 - Write to file

Result

v0
contains number of characters written (negative if error)

Arguments

a0
file descriptor
a1
address of output buffer
a2
number of characters to write

93 - Exit2 (terminate with value)

Service 93 - If the RISCV program is run under control of the MARS graphical interface (GUI), the exit code in a0 is ignored.

Arguments

a0
termination result

1024 - Open file

Service 1024 - MARS implements three flag values: 0 for read-only, 1 for write-only with create, and 9 for write-only with create and append. It ignores mode. The returned file descriptor will be negative if the operation failed. MARS maintains file descriptors internally and allocates them starting with 3. File descriptors 0, 1 and 2 are always open for: reading from standard input, writing to standard output, and writing to standard error, respectively (new in release 4.3).

Result

v0
contains file descriptor (negative if error)

Arguments

a0
address of null-terminated string containing filename
a1
flags
a2
mode