DIVU: RISC-V instruction reference

divuDivide unsigned 
Divides the second register by the third as unsigned integers and stores the quotient in the first.
RISC-V manual: divu 
Used in Arithmetic, logic and bitsRISC-V assembly
Flappy ASMRISC-V assembly
 
Forms  divu , ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
t2 An integer register. It may be the same register as t1. 
t3 An integer register. It may be the same register as t1. 
 .text
li t0, 18
li t1, 5
# t0=18, t1=5; divu writes 3 to t2.
divu t2, t0, t1