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csrci

Clear bits in CSR immediate Pseudo-instruction

Clears the CSR bits that are set in a 5-bit constant, leaving the other bits unchanged.

RISC-V manual: csrrci

Forms

Operands

csr
A control and status register, written by name or number, such as fcsr, fflags, frm, cycle, time, instret, ustatus, uepc, ucause or utval. See the supported registers.
imm12
A signed 12-bit immediate, -2048 to 2047. 
# Initialize fcsr to 1; csrci uses immediate 1 and leaves fcsr=0.
.text
li t3, 1
csrw t3, fcsr
csrci fcsr, 1
csrr t2, fcsr