CSRR - RISC-V instruction reference

csrrRead control and status register Pseudo-instruction
Reads the CSR into t1 without writing to it.
Forms  csrr ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
csr A control and status register, written by name or number, such as fcsr, fflags, frm, cycle, time, instret, ustatus, uepc, ucause or utval. See the supported registers. 
 # Clear fcsr with the documented alias, then read it with csrr. t0 is 0.
.text
li t1, 0
csrw t1, fcsr
csrr t0, fcsr