addw

Operands

reg, reg, reg

Addition: set t1 to (t2 plus t3) using only the lower 32 bits (64bit)

Addition: set t1 to (t2 plus t3) using only the lower 32 bits (64bit) addw t1,t2,t3

This example runs on RV64.

.text
li t0, 2147483647
li t1, 1
# t0=2147483647, t1=1; addw writes -2147483648 (0xFFFFFFFF80000000) to t2.
addw t2, t0, t1
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