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RISC-V

Directives

Screen and I/O

Syscalls

Registers

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addw

Operands

reg, reg, reg

Addition: set t1 to (t2 plus t3) using only the lower 32 bits (64bit)

Variants

Addition: set t1 to (t2 plus t3) using only the lower 32 bits (64bit) addw t1,t2,t3

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