REMW: RISC-V instruction reference

remwRemainder word (32-bit) RV64 only
Sets the first register to the remainder of the low 32 bits of the second divided by those of the third, as signed values, sign-extended.
RISC-V manual: remw 
Forms  remw , ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
t2 An integer register. It may be the same register as t1. 
t3 An integer register. It may be the same register as t1. 
This example runs on RV64.
 .text
li t0, 18
li t1, 5
# t0=18, t1=5; remw writes 3 to t2.
remw t2, t0, t1