NEGW: RISC-V instruction reference

negwNegate word (32-bit) Pseudo-instructionRV64 only
Sets the first register to the negation of the low 32 bits of the second, sign-extended.
RISC-V manual: subw 
Forms  negw ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
t2 An integer register. It may be the same register as t1. 
This example runs on RV64.
 .text
li t0, 13
# t0=13; negw writes -13 (0xFFFFFFFFFFFFFFF3) to t2.
negw t2, t0