DIVUW: RISC-V instruction reference

divuwDivide unsigned word (32-bit) RV64 only
Divides the low 32 bits of the second register by those of the third as unsigned values and sign-extends the quotient into the first.
RISC-V manual: divuw 
Forms  divuw , ,   
Operands t1 Any integer register, x0 to x31, or its named alias, such as zero, t0 or t6. 
t2 An integer register. It may be the same register as t1. 
t3 An integer register. It may be the same register as t1. 
This example runs on RV64.
 .text
li t0, 18
li t1, 5
# t0=18, t1=5; divuw writes 3 to t2.
divuw t2, t0, t1