Division: set t1 to the result of t2/t3 using unsigned division limited to 32 bits (64bit)
divuw
Operands
reg, reg, regVariants
- Division: set t1 to the result of t2/t3 using unsigned division limited to 32 bits (64bit) divuw t1,t2,t3
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Division: set t1 to the result of t2/t3 using unsigned division limited to 32 bits (64bit)